Epyc

Not to be confused with Epic.

Epyc (stylized as EPYC) is a brand of multi-core x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Introduced in June 2017, they are specifically targeted for the server and embedded system markets.^[1]

Epyc

General information
Launched	June 20, 2017; 7 years ago (2017-06-20)
Marketed by	AMD
Designed by	AMD
Common manufacturers	GlobalFoundries (14 nm and 12 nm) TSMC (7 nm and beyond)
Performance
Max. CPU clock rate	2.7 GHz to 5.0 GHz
Architecture and classification
Technology node	14 nm to 3 nm
Microarchitecture	Zen microarchitecture: Zen Zen 2 Zen 3 Zen 4 Zen 4c Zen 5 Zen 5c
Instruction set	AMD64 (x86-64)
Extensions	MMX(+), SSE1, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, AVX2, AVX-512 (with Zen 4 and later), FMA3, CVT16/F16C, ABM, BMI1, BMI2, AES, CLMUL, RDRAND, SHA, SME, AMD-V, AMD-Vi
Physical specifications
Cores	up to 192 cores/384 threads per socket
Memory (RAM)	up to 12 memory channels at 6400 MT/s
Socket	SP3 SP5 SP6
Products, models, variants
Core names	Naples Rome Milan Genoa Bergamo Siena Turin
History
Predecessor	Opteron

Epyc processors share the same microarchitecture as their regular desktop-grade counterparts, but have enterprise-grade features such as higher core counts, more PCI Express lanes, support for larger amounts of RAM, and larger cache memory. They also support multi-chip and dual-socket system configurations by using the Infinity Fabric interconnect.

History

In March 2017, AMD announced plans to re-enter the server market with a platform based on the Zen microarchitecture, codenamed Naples, and officially revealed it under the brand name Epyc in May.^[2] That June AMD officially launched Epyc 7001 series processors, offering up to 32 cores per socket, and enabling performance that allowed Epyc to be competitive with the competing Intel Xeon Scalable product line.^[3] In August 2019, the Epyc 7002 "Rome" series processors, based on the Zen 2 microarchitecture, launched, doubling the core count per socket to 64, and increasing per-core performance dramatically over the last generation architecture.

In March 2021, AMD launched the Epyc 7003 "Milan" series, based on the Zen 3 microarchitecture.^[4] Epyc Milan brought the same 64 cores as Epyc Rome, but with much higher per-core performance, with the Epyc 7763 beating the Epyc 7702 by up to 22 percent despite having the same number of cores and threads.^[5] A refresh of the Epyc 7003 "Milan" series with 3D V-Cache, named Milan-X, launched on March 21, 2022, using the same cores as Milan, but with an additional 512 MB of cache stacked onto the compute dies, bringing the total amount of cache per CPU to 768 MB.^[6]

In September 2021, Oak Ridge National Laboratory partnered with AMD and HPE Cray to build Frontier, a supercomputer with 9,472 Epyc 7453 CPUs and 37,888 Instinct MI250X GPUs, becoming operational by May 2022. As of November 2023, it is the most powerful supercomputer in the world according to the TOP500, with a peak performance of over 1.6 exaFLOPS.

In November 2021, AMD detailed the upcoming generations of Epyc, and unveiled the new LGA-6096 SP5 socket that would support the new generations of Epyc chips. Codenamed Genoa, these CPUs are based on the Zen 4 microarchitecture and built on TSMC's N5 node, supporting up to 96 cores and 192 threads per socket, alongside 12 channels of DDR5^[7] and 128 PCIe 5.0 lanes. Genoa also became the first x86 server CPU to support Compute Express Link 1.1,^[8] or CXL, allowing for further expansion of memory and other devices with a high bandwidth interface built on PCIe 5.0. AMD also shared information regarding the sister chip of Genoa, codenamed Bergamo. Bergamo is based on a modified version of Zen 4 named Zen 4c, designed to allow for much higher core counts and efficiency at the cost of lower single-core performance, targeting cloud providers and workloads, compared to traditional high performance computing workloads.^[9] It is compatible with Socket SP5, and supports up to 128 cores and 256 threads per socket.^[10]

In November 2022, AMD launched their 4th generation Epyc "Genoa" series of CPUs. Some tech reviewers and customers had already received hardware for testing and benchmarking, and third party benchmarks of Genoa parts were immediately available. The flagship part, the 96 core Epyc 9654, set records for multi-core performance, and showed up to 4× performance compared to Intel's flagship part, the Xeon Platinum 8380. High memory bandwidth and extensive PCIe connectivity removed many bottlenecks, allowing all 96 cores to be utilized in workloads where previous generation Milan chips would have been I/O-bound.

In June 2023, AMD began shipping the 3D V-Cache enabled Genoa-X lineup, a variant of Genoa that uses the same 3D die stacking technology as Milan-X to enable up to 1152 MB of L3 cache, a 50% increase over Milan-X, which had a maximum of 768 MB of L3 cache.^[11] On the same day, AMD also announced the release of their cloud optimized Zen 4c SKUs, codenamed Bergamo, offering up to 128 cores per socket, utilizing a modified version of the Zen 4 core that was optimized for power efficiency and to reduce die space. Zen 4c cores do not have any instructions removed compared to standard Zen 4 cores; instead, the amount of L3 cache per CCX is reduced from 32 MB to 16 MB, and the frequency of the cores is reduced.^[12] Bergamo is socket compatible with Genoa, using the same SP5 socket and supporting the same CXL, PCIe, and DDR5 capacity as Genoa.^[13]

In September 2023, AMD launched their low power and embedded 8004 series of CPUs, codenamed Siena. Siena utilizes a new socket, called SP6, which has a smaller footprint and pin count than the SP5 socket of its contemporary Genoa processors. Siena utilizes the same Zen 4c core architecture as Bergamo cloud native processors, allowing up to 64 cores per processor, and the same 6 nm I/O die as Bergamo and Genoa, although certain features have been cut down, such as reducing the memory support from 12 channels of DDR5 to only 6, and removing dual socket support.^[14]

On October 10th, 2024, AMD launched the new 9005 series of CPUs, codenamed Turin. Sharing the same SP5 socket as Genoa and Bergamo, Turin came with numerous platform advancements, including the support for up to 6400 MT/s DDR5 memory.^[15] Turin also increased the core count and frequency offerings, with Turin offering 128 Zen 5 cores per socket, and Turin Dense offering 192 Zen 5c cores per socket. And with the highest frequency SKU (The EPYC 9575F) having a operating frequency of up to 5 GHz.^[16]

AMD Epyc CPU codenames follow the naming scheme of Italian cities, including Milan, Rome, Naples, Genoa, Bergamo, Siena, Turin and Venice.

AMD Epyc CPU generations^{[17][18][19][20][21]}

Gen	Year	Codename	Product line	Cores	Socket	Memory
Server
1st	2017	Naples	7001 series	32 × Zen	SP3 (LGA)	DDR4
2nd	2019	Rome	7002 series	64 × Zen 2
3rd	2021	Milan	7003 series	64 × Zen 3
	2022	Milan-X
4th		Genoa	9004 series	96 × Zen 4	SP5 (LGA)	DDR5
	2023	Genoa-X
		Bergamo		128 × Zen 4c
		Siena	8004 series	64 × Zen 4c	SP6 (LGA)
5th	2024	Turin	9005 series	128 × Zen 5	SP5 (LGA)
		Turin Dense		192 × Zen 5c
6th	TBA	Venice	TBA	TBA	SP7 (LGA)	TBA
Embedded
1st	2018	Snowy Owl	Embedded 3001 series	16 × Zen	SP4 (BGA)	DDR4
2nd	2019	Naples	Embedded 7001 series	32 × Zen	SP3 (BGA)
3rd	2021	Rome	Embedded 7002 series	64 × Zen 2
4th	2023	Genoa	Embedded 9004 series	96 × Zen 4	SP5 (BGA)	DDR5

Design

A delidded second gen Epyc 7702, showing the die configuration

Epyc CPUs use a multi-chip module design to enable higher yields for a CPU than traditional monolithic dies. First generation Epyc CPUs are composed of four 14 nm compute dies, each with up to 8 cores.^[22][23] Cores are symmetrically disabled on dies to create lower binned products with fewer cores but the same I/O and memory footprint. Second and Third gen Epyc CPUs are composed of eight compute dies built on a 7 nm process node, and a large input/output (I/O) die built on a 14 nm process node.^[24] Third gen Milan-X CPUs use advanced through-silicon-vias to stack an additional die on top of each of the 8 compute dies, adding 64 MB of L3 cache per die.^[25]

Epyc CPUs supports both single socket and dual socket operation. In a dual socket configuration, 64 PCIe lanes from each CPU are allocated to AMD's proprietary Infinity Fabric interconnect to allow for full bandwidth between both CPUs.^[26] Thus, a dual socket configuration has the same number of usable PCIe lanes as a single socket configuration. First generation Epyc CPUs had 128 PCIe 3.0 lanes, while second and third generation had 128 PCIe 4.0 lanes. All current Epyc CPUs are equipped with up to eight channels of DDR4 at varying speeds, though next gen Genoa CPUs are confirmed by AMD to support up to twelve channels of DDR5.^[7][27]

Unlike Opteron, Intel equivalents and AMD's desktop processors (excluding Socket AM1), Epyc processors are chipset-free - also known as system on a chip. That means most features required to make servers fully functional (such as memory, PCI Express, SATA controllers, etc.) are fully integrated into the processor, eliminating the need for a chipset to be placed on the mainboard. Some features may require the use of additional controller chips to utilize.

A near-infrared photograph of a delidded second gen Epyc 7702. Each CCD has two CCXs

Reception

Initial reception to Epyc was generally positive.^[27] Epyc was generally found to outperform Intel CPUs in cases where the cores could work independently, such as in high-performance computing and big-data applications. First generation Epyc fell behind in database tasks compared to Intel's Xeon parts due to higher cache latency.^[27] In 2021 Meta Platforms selected Epyc chips for its metaverse data centers.^[28]

Epyc Genoa was well received, as it offered improved performance and efficiency compared to previous offerings, though received some criticism for not having 2 DIMMs per channel configurations validating, with some reviewers calling it an "incomplete platform".^[29]

List of Epyc processors

Server

First generation Epyc (Naples)

The following table lists the devices using the first generation design.

A "P" suffix denotes support for only a single socket configuration. Non-P models use 64 PCIe lanes from each processor for the communication between processors.

EPYC 7001 series

Common features:

• SP3 socket
• Zen microarchitecture
• GloFo 14 nm process
• MCM with four SOC^[30] dies, two core complexes (CCX) per die with up to 4 cores and 8 MiB of L3 cache per CCX
• Eight-channel DDR4-2666 (7251 limited to DDR4-2400)
• 128 PCIe 3.0 lanes per socket, 64 of which are used for Infinity Fabric in 2P platforms

Model[lower-roman 1]	Cores (threads)	Chiplets	Core config[lower-roman 2]	Clock rate (GHz)			Cache			TDP	Release		Embedded options[lower-roman 3]
				Base	Boost		L2 (per core)	L3 (per CCX)	Total		Date	Price (USD)
					All–core	Max
7251[31][32]	8 (16)	4[30]	8 × 1	2.1	2.9	2.9	512 KiB	4 MiB	36 MiB	120 W	Jun 2017[33]	$475	Yes
7261[31][34]				2.5				8 MiB	68 MiB	155/170 W	Jun 2018[35]	$570	Yes
7281[31][32]	16 (32)		8 × 2	2.1	2.7	2.7		4 MiB	40 MiB	155/170 W	Jun 2017[33]	$650	Yes
7301[31][32]				2.2				8 MiB	72 MiB			$800	Yes
7351P[31][32]				2.4	2.9	2.9						$750	735P
7351[31][32]												$1,100	Yes
7371[31][36]				3.1	3.6	3.8				200 W	Nov 2018[37]	$1,550	Yes
7401P[31][32]	24 (48)		8 × 3	2.0	2.8	3.0		8 MiB	76 MiB	155/170 W	Jun 2017[33]	$1,075	740P
7401[31][32]												$1,850	Yes
7451[31][32]				2.3	2.9	3.2				180 W		$2,400	Yes
7501[31][32]	32 (64)		8 × 4	2.0	2.6	3.0		8 MiB	80 MiB	155/170 W		$3,400	Yes
7551P[31][32]					2.55					180 W		$2,100	755P
7551[31][32]												$3,400	Yes
7571[38][39]				2.2	3.0					200 W	Nov 2018	OEM/AWS	--
7601[31][32]					2.7	3.2				180 W	Jun 2017[33]	$4,200	Yes

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1. Models with "P" suffixes are uniprocessors, only available as single socket configuration.
2. Core Complexes (CCX) × cores per CCX
3. Epyc embedded 7001 series models have identical specifications as Epyc 7001 series.

A Epyc 7001 die configuration

A second generation Epyc CPU in an SP3 socket

Second generation Epyc (Rome)

First generation Epyc processor

In November 2018, AMD announced Epyc 2 at their Next Horizon event, the second generation of Epyc processors codenamed "Rome" and based on the Zen 2 microarchitecture.^[40] The processors feature up to eight 7 nm-based "chiplet" processors with a 14 nm-based IO chip providing 128 PCIe 4.0 lanes in the center interconnected via Infinity Fabric. The processors support up to 8 channels of DDR4 RAM up to 4 TB, and introduce support for PCIe 4.0. These processors have up to 64 cores with 128 SMT threads per socket.^[41] The 7 nm "Rome" is manufactured by TSMC.^[24] It was released on August 7, 2019.^[42] It has 39.5 billion transistors.^[43]

In April 2020, AMD launched three new SKUs using Epyc’s 7nm Rome platform. The three processors introduced were the eight-core Epyc 7F32, the 16-core 7F52 and the 24-core 7F72, featuring base clocks up to 3.7 GHz (up to 3.9 GHz with boost) within a TDP range of 180 to 240 watts. The launch was supported by Dell EMC, Hewlett Packard Enterprise, Lenovo, Supermicro, and Nutanix.^[44]

EPYC 7002 series

Common features:

• SP3 socket
• Zen 2 microarchitecture
• TSMC 7 nm process for the compute dies, GloFo 14 nm process for the I/O die
• MCM with one I/O Die (IOD) and multiple Core Complex Dies (CCD) for compute, two core complexes (CCX) per CCD chiplet
• Eight-channel DDR4-3200
• 128 PCIe 4.0 lanes per socket, 64 of which are used for Infinity Fabric in 2P platforms

Model	Cores (threads)	Chiplets	Core config[lower-roman 1]	Clock rate		Cache			Socket	Scaling	TDP	Release date	Release price
				Base (GHz)	Boost (GHz)	L2 (per core)	L3 (per CCX)	Total
7232P	8 (16)	2 + IOD	4 × 2	3.1	3.2	512 KiB	8 MiB	36 MiB	SP3	1P	120 W	Aug 7, 2019	$450
7252			4 × 2	3.1	3.2		16 MiB	68 MiB		2P			$475
7262		4 + IOD	8 × 1	3.2	3.4			132 MiB			155 W		$575
7F32			8 × 1	3.7	3.9			132 MiB			180 W	Apr 14, 2020[45]	$2100
7272	12 (24)	2 + IOD	4 × 3	2.9	3.2		16 MiB	70 MiB		2P	120 W	Aug 7, 2019	$625
7282	16 (32)	2 + IOD	4 × 4	2.8	3.2		16 MiB	72 MiB					$650
7302P		4 + IOD	8 × 2	3	3.3			136 MiB		1P	155 W		$825
7302										2P			$978
7F52		8 + IOD	16 × 1	3.5	3.9			264 MiB			240 W	Apr 14, 2020[45]	$3100
7352	24 (48)	4 + IOD	8 × 3	2.3	3.2		16 MiB	140 MiB		2P	155 W	Aug 7, 2019	$1350
7402P				2.8	3.35					1P	180 W		$1250
7402										2P			$1783
7F72		6 + IOD	12 × 2	3.2	3.7			204 MiB			240 W	Apr 14, 2020[45]	$2450
7452	32 (64)	4 + IOD	8 × 4	2.35	3.35		16 MiB	144 MiB		2P	155 W	Aug 7, 2019	$2025
7502P				2.5	3.35					1P	180 W		$2300
7502										2P			$2600
7542				2.9	3.4						225 W		$3400
7532		8 + IOD	16 × 2	2.4	3.3			272 MiB			200 W		$3350
7552	48 (96)	6 + IOD	12 × 4	2.2	3.3		16 MiB	216 MiB		2P	200 W		$4025
7642		8 + IOD	16 × 3	2.3	3.3			280 MiB			225 W		$4775
7662	64 (128)	8 + IOD	16 × 4	2.0	3.3		16 MiB	288 MiB		2P	225 W		$6150
7702P				2	3.35					1P	200 W		$4425
7702										2P			$6450
7742				2.25	3.4						225 W		$6950
7H12				2.6	3.3						280 W	Sep 18, 2019	---

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1. Core Complexes (CCX) × cores per CCX

The bottom side of an Epyc 7302 mounted in a plastic carrier

Third generation Epyc (Milan)

At the HPC-AI Advisory Council in the United Kingdom in October 2019, AMD stated specifications for Milan, Epyc chips based on the Zen 3 microarchitecture.^[46] Milan chips will use Socket SP3, with up to 64 cores on package, and support eight-channel DDR4 RAM and 128 PCIe 4.0 lanes.^[46] It also announced plans for the subsequent generation of chips, codenamed Genoa, that will be based on the Zen 4 microarchitecture and use Socket SP5.^[46]

Milan CPUs were launched by AMD on March 15, 2021.^[47]

Milan-X CPUs were launched March 21, 2022.^[6] They use 3D V-Cache technology to increase the maximum L3 cache per socket capacity from 256 MB to 768 MB.^[48][49][50]

EPYC 7003 series

Common features:

• SP3 socket
• Zen 3 microarchitecture
• TSMC 7 nm process for the compute and cache dies, GloFo 14 nm process for the I/O die
• MCM with one I/O Die (IOD) and multiple Core Complex Dies (CCD) for compute, one core complex (CCX) per CCD chiplet
• Eight-channel DDR4-3200
• 128 PCIe 4.0 lanes per socket, 64 of which are used for Infinity Fabric in 2P platforms
• 7003X series models include 64 MiB L3 cache dies stacked on top of the compute dies (3D V-Cache)
• 7003P series models are restricted to uniprocessor operation (1P)

Model	Cores (threads)	Chiplets	Core config [lower-roman 1]	Clock rate		Cache			Socket	Scaling	TDP	Release price
				Base (GHz)	Boost (GHz)	L2 (per core)	L3 (per CCX)	Total
7203(P)	8 (16)	2 + IOD	2 × 4	2.8	3.4	512 KiB	32 MiB	68 MiB	SP3	2P (1P)	120 W	$348 ($338)
72F3		8 + IOD	8 × 1	3.7	4.1			260 MiB		2P	180 W	$2468
7303(P)	16 (32)	2 + IOD	2 × 8	2.4	3.4		32 MiB	72 MiB		2P (1P)	130 W	$604 ($594)
7313(P)		4 + IOD	4 × 4	3.0	3.7			136 MiB		2P (1P)	155 W	$1083 ($913)
7343				3.2	3.9					2P	190 W	$1565
73F3		8 + IOD	8 × 2	3.5	4.0			264 MiB			240 W	$3521
7373X		8* + IOD		3.05	3.8		96 MiB	776 MiB				$4185
7413	24 (48)	4 + IOD	4 × 6	2.65	3.6		32 MiB	140 MiB		2P	180 W	$1825
7443(P)				2.85	4.0					2P (1P)	200 W	$2010 ($1337)
74F3		8 + IOD	8 × 3	3.2	4.0			268 MiB		2P	240 W	$2900
7473X		8* + IOD		2.8	3.7		96 MiB	780 MiB				$3900
7453	28 (56)	4 + IOD	4 × 7	2.75	3.45		16 MiB	78 MiB		2P	225 W	$1570
7513	32 (64)	8 + IOD	8 × 4	2.6	3.65		16 MiB	144 MiB		2P	200 W	$2840
7543(P)				2.8	3.7		32 MiB	272 MiB		2P (1P)	225 W	$3761 ($2730)
75F3				2.95	4.0					2P	280 W	$4860
7573X		8* + IOD		2.8	3.6		96 MiB	784 MiB				$5590
7643(P)	48 (96)	8 + IOD	8 × 6	2.3	3.6		32 MiB	280 MiB		2P (1P)	225 W	$4995 ($2722)
7663(P)	56 (112)		8 × 7	2.0	3.5		32 MiB	284 MiB		2P (1P)	240 W	$6366 ($3139)
7713(P)	64 (128)		8 × 8	2.0	3.675		32 MiB	288 MiB		2P (1P)	225 W	$7060 ($5010)
7763				2.45	3.4					2P	280 W	$7890
7773X		8* + IOD		2.2	3.5		96 MiB	800 MiB				$8800

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1. Core Complexes (CCX) × cores per CCX

Fourth generation Epyc (Genoa, Bergamo and Siena)

On November 10, 2022, AMD launched the fourth generation of Epyc server and data center processors based on the Zen 4 microarchitecture, codenamed Genoa.^[51] At their launch event, AMD announced that Microsoft and Google would be some of Genoa's customers.^[52] Genoa features between 16 and 96 cores with support for PCIe 5.0 and DDR5. There was also an emphasis by AMD on Genoa's energy efficiency, which according to AMD CEO Lisa Su, means "lower total cost of ownership" for enterprise and cloud datacenter clients.^[53] Genoa uses AMD's new SP5 (LGA 6096) socket.^[54]

On June 13, 2023, AMD introduced Genoa-X with 3D V-Cache technology for technical computing performance and Bergamo (9734, 9754 and 9754S) for cloud native computing.^[55]

On September 18, 2023, AMD introduced the low power Siena lineup of processors, based on the Zen 4c microarchitecture. Siena supports up to 64 cores on the new SP6 socket, which is currently only used by Siena processors. Siena uses the same I/O die as Bergamo, however certain features, such as dual socket support, are removed, and other features are reduced, such as the change from 12 channel memory support to 6 channel memory support.^[56]

Model	Fab	Cores (Threads)	Chiplets	Core config[lower-roman 1]	Clock rate (GHz)		Cache (MB)			Socket	Socket count	PCIe 5.0 lanes	Memory support	TDP	Release date	Price (USD)
					Base	Boost	L1	L2	L3				DDR5 ECC
Low Power & Edge (Zen 4c cores)
8024P	TSMC N5	8 (16)	4 × CCD 1 × I/OD	4 × 2	2.4	3.0	0.5	8	32	SP6	1P	96	DDR5-4800 six-channel	90 W	Sep 18, 2023	$409
8024PN					2.05									80 W		$525
8124P		16 (32)		4 × 4	2.45		1	16	64					125 W		$639
8124PN					2.0									100 W		$790
8224P		24 (48)		4 × 6	2.55		1.5	24						160 W		$855
8224PN					2.0									120 W		$1,015
8324P		32 (64)		4 × 8	2.65		2	32	128					180 W		$1,895
8324PN					2.05									130 W		$2,125
8434P		48 (96)		4 × 12	2.5	3.1	3	48						200 W		$2,700
8434PN					2.0	3.0								155 W		$3,150
8534P		64 (128)		4 × 16	2.3	3.1	4	64						200 W		$4,950
8534PN					2.0									175 W		$5,450
Mainstream Enterprise (Zen 4 cores)
9124	TSMC N5	16 (32)	4 × CCD 1 × I/OD	4 × 4	3.0	3.7	1	16	64	SP5	1P/2P	128	DDR5-4800 twelve-channel	200 W	Nov 10, 2022	$1,083
9224		24 (48)		4 × 6	2.5	3.7	1.5	24						200 W		$1,825
9254				4 × 6	2.9	4.15			128					220 W		$2,299
9334		32 (64)		4 × 8	2.7	3.9	2	32						210 W		$2,990
9354			8 × CCD 1 × I/OD	8 × 4	3.25	3.75			256					280 W		$3,420
9354P											1P					$2,730
Performance Enterprise (Zen 4 cores)
9174F	TSMC N5	16 (32)	8 × CCD 1 × I/OD	8 × 2	4.1	4.4	1	16	256	SP5	1P/2P	128	DDR5-4800 twelve-channel	320 W	Nov 10, 2022	$3,850
9184X					3.55	4.2			768						Jun 13, 2023	$4,928
9274F		24 (48)		8 × 3	4.05	4.3	1.5	24	256						Nov 10, 2022	$3,060
9374F		32 (64)		8 × 4	3.85	4.3	2	32								$4,860
9384X					3.1	3.9			768						Jun 13, 2023	$5,529
9474F		48 (96)		8 × 6	3.6	4.1	3	48	256					360 W	Nov 10, 2022	$6,780
High Performance Computing (Zen 4 cores)
9454	TSMC N5	48 (96)	8 × CCD 1 × I/OD	8 × 6	2.75	3.8	3	48	256	SP5	1P/2P	128	DDR5-4800 twelve-channel	290 W	Nov 10, 2022	$5,225
9454P											1P					$4,598
9534		64 (128)		8 × 8	2.45	3.7	4	64			1P/2P			280 W		$8,803
9554					3.1	3.75								360 W		$9,087
9554P											1P					$7,104
9634		84 (168)	12 × CCD 1 × I/OD	12 × 7	2.25	3.7	5.25	84	384		1P/2P			290 W		$10,304
9654		96 (192)		12 × 8	2.4	3.7	6	96						360 W		$11,805
9654P											1P					$10,625
9684X					2.55	3.7			1152		1P/2P			400 W	Jun 13, 2023	$14,756
Cloud (Zen 4c cores)
9734	TSMC N5	112 (224)	8 × CCD 1 × I/OD	8 × 14	2.2	3.0	7	112	256	SP5	1P/2P	128	DDR5-4800 twelve-channel	340 W	Jun 13, 2023	$9,600
9754S		128 (128)		8 × 16	2.25	3.1	8	128						360 W		$10,200
9754		128 (256)														$11,900

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1. Core Complexes (CCX) × cores per CCX

Fifth generation Epyc (Turin and Turin Dense)

The fifth generation of Epyc processors were showcased by AMD at Computex 2024 on June 3. Named the Epyc 9005 series, it will come in two variants:^[57]

• Zen 5 based, up to 128 cores and 256 threads, built on TSMC N3E process
• Zen 5c based, up to 192 cores and 384 threads, built on TSMC N4X process

Both variants are officially referred to under the Turin codename by AMD, although the nickname of "Turin Dense" has also been used to refer to the Zen 5c based CPUs.^[58]

Both of these processor series will be socket-compatible with the SP5 socket used by Genoa and Bergamo. Epyc 9005 series were launched in 10 October 2024 at AMD's Advancing AI event 2024.^[59]

Model	Fab	Cores (Threads)	Chiplets	Core config[lower-roman 1]	Clock rate (GHz)		Cache (MB)			Socket	Socket count	PCIe 5.0 lanes	Memory support	TDP	Release date	Release price (USD)
					Base	Boost	L1 Per Core	L2 Per Core	L3 Shared
Turin Dense (Zen 5c cores)
9645	TSMC N3E	96 (192)	8 × CCD 1 × I/OD	8 × 12	2.3	3.7	80 KB	1 MB	256 MB	SP5	1P/2P	128 (160 in 2-socket systems)	DDR5-6400 twelve-channel	320 W	October 10, 2024	$11048
9745		128 (256)		8 × 16	2.4									400 W		$12141
9825		144 (288)	12 × CCD 1 × I/OD	12 × 12	2.2				384 MB					390 W		$13006
9845		160 (320)	10 × CCD 1 × I/OD	10 × 16	2.1				320 MB					390 W		$13564
9965		192 (384)	12 × CCD 1 × I/OD	12 × 16	2.25				384 MB					500 W		$14813
Turin (Zen 5 cores)
9015	TSMC N4X	8 (16)	2 × CCD 1 × I/OD	2 × 4	3.6	4.1	80 KB	1 MB	64 MB	SP5	1P/2P	128 (160 in 2-socket systems)	DDR5-6400 twelve-channel	125 W	October 10, 2024	$527
9115		16 (32)		2 × 8	2.6	4.1								125 W		$726
9135		16 (32)			3.65	4.3								200 W		$1214
9175F		16 (32)	16 × CCD 1 × I/OD	16 × 1	4.2	5.0			512 MB					320 W		$4256
9255		24 (48)	4 × CCD 1 × I/OD	4 × 6	3.25	4.3			128 MB					200 W		$2495
9275F		24 (48)	8 × CCD 1 × I/OD	8 × 3	4.1	4.8			256 MB					320 W		$3439
9335		32 (64)	4 × CCD 1 × I/OD	4 × 8	3.0	4.4			128 MB					210 W		$3178
9355P		32 (64)	8 × CCD 1 × I/OD	8 × 4	3.55	4.4			256 MB		1P	128		280 W		$2998
9355		32 (64)			3.55	4.4					1P/2P	128 (160 in 2-socket systems)		280 W		$3694
9375F		32 (64)			3.8	4.8								320 W		$5306
9365		36 (72)	6 × CCD 1 × I/OD	6 × 6	3.4	4.3			192 MB					300 W		$4341
9455P		48 (96)	8 × CCD 1 × I/OD	8 × 6	3.15	4.4			256 MB		1P	128		300 W		$4819
9455		48 (96)			3.15	4.4					1P/2P	128 (160 in 2-socket systems)		300 W		$5412
9475F		48 (96)			3.65	4.8								400 W		$7592
9535		64 (128)		8 × 8	2.4	4.3								300 W		$8992
9555P		64 (128)			3.2	4.4					1P	128		360 W		$7983
9555		64 (128)			3.2	4.4					1P/2P	128 (160 in 2-socket systems)		360 W		$9826
9575F		64 (128)			3.3	5.0								400 W		$11791
9565		72 (144)	12 × CCD 1 × I/OD	12 × 6	3.15	4.3			384 MB					400 W		$10468
9655P		96 (192)		12 × 8	2.5	4.5					1P	128		400 W		$10811
9655		96 (192)			2.5	4.5					1P/2P	128 (160 in 2-socket systems)		400 W		$11852
9755		128 (256)	16 × CCD 1 × I/OD	16 × 8	2.7	4.1			512 MB					500 W		$12984

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1. Core Complexes (CCX) × cores per CCX

Embedded

First generation Epyc (Snowy Owl)

In February 2018, AMD also announced the Epyc 3000 series of embedded Zen CPUs.^[60]

Common features of EPYC Embedded 3000 series CPUs:

• Socket: SP4 (31xx and 32xx models use SP4r2 package).
• All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
• Fabrication process: GlobalFoundries 14 nm.

Model	Cores (threads)	Clock rate (GHz)			L3 cache (total)	TDP	Chiplets	Core config[lower-roman 1]	Release date
		Base	Boost
			All-core	Max
3101[61]	4 (4)	2.1	2.9	2.9	8 MB	35 W	1 × CCD	1 × 4	Feb 2018
3151[61]	4 (8)	2.7			16 MB	45 W		2 × 2
3201[61]	8 (8)	1.5	3.1	3.1		30 W		2 × 4
3251[61]	8 (16)	2.5				55 W
3255[62]						25–55 W			Dec 2018
3301[61]	12 (12)	2.0	2.15	3.0	32 MB	65 W	2 × CCD	4 × 3	Feb 2018
3351[61]	12 (24)	1.9	2.75			60–80 W
3401[61]	16 (16)	1.85	2.25			85 W		4 × 4
3451[61]	16 (32)	2.15	2.45			80–100 W

• v
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1. Core Complexes (CCX) × cores per CCX

Chinese variants

Main article: Hygon Information Technology

A variant created for the Chinese server market by Hygon Information Technology is the Hygon Dhyana system on a chip.^[63][64] It is noted to be a variant of the AMD Epyc, and is so similar that "there is little to no differentiation between the chips".^[63] It has been noted that there is "less than 200 lines of new kernel code" for Linux kernel support, and that the Dhyana is "mostly a re-branded Zen CPU for the Chinese server market".^[64] Later benchmarks showed that certain floating point instructions are performing worse, probably to comply with US export restrictions.^[65] AES and other western cryptography algorithms are replaced by Chinese variants throughout the design.^[65]

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