Zen (first generation)

Zen is the first iteration in the Zen family of computer processor microarchitectures from AMD. It was first used with their Ryzen series of CPUs in February 2017.^[4] The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs, codenamed "Summit Ridge", reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017^[11] and Zen-based APUs arrived in November 2017.^[12]

AMD Zen

The logo for the Zen microarchitecture is a closed ensō
General information
Launched	March 2, 2017; 8 years ago (March 2, 2017)[1]
Designed by	AMD
Common manufacturer	GlobalFoundries[2]
CPUID code	Family 17h
Cache
L1 cache	64 KB instruction, 32 KB data per core
L2 cache	512 KB per core
L3 cache	8 MB per CCX (APU: 4 MB)
Architecture and classification
Technology node	14 nm (FinFET)[2]
Instruction set	AMD64 (x86-64)
Physical specifications
Transistors	4.8 billion per 8-core "Zeppelin" die[3]
Cores	2–4 (essential) 4–8 (mainstream) 8–16 (enthusiast)[4][5][6][7] Up to 32 (server)[4][8]
Sockets	Socket AM4[9] Socket TR4 Socket SP3
Products, models, variants
Product code names	Summit Ridge (Desktop) Whitehaven (HEDT) Raven Ridge (APU/Embedded) Naples (Server CPU) Snowy Owl (Server APU)[10]
Brand names	Ryzen Ryzen Threadripper Epyc Athlon
History
Predecessor	Excavator (4th gen)
Successor	Zen+
Support status
Supported

Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 memory and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket;^[13][14] and Epyc server processors offer 128 PCIe 3.0 lanes and octa-channel DDR4 using the SP3 socket.

Zen is based on a SoC design.^[15] The memory controller and the PCIe, SATA, and USB controllers are incorporated into the same chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area.^[16] This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.

By 2020, 260 million Zen cores have already been shipped by AMD.^[17]

Design

A highly simplified illustration of the Zen microarchitecture: a core has a total of 512 KB of L2 cache.

Ryzen 3 1200 die shot

Photomontage of a delidded Zen CPU with an etched die

A delidded AMD EPYC 7001 processor used in servers. The four dies are similar to the ones used in mainstream processors. All EPYC processors contain four dies to provide structural support to the IHS (Integrated Heat Spreader).^[18][19][20]

A delidded AMD Athlon 3000G APU, based on the Zen architecture. The die is physically smaller than those on mainstream Zen processors.

Die shot of an AMD Athlon 3000G

According to AMD, the main focus of Zen is on increasing per-core performance.^[21][22][23]

New or improved features include:^[24]

• The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth.
• SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors.^[25]
• A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric.^[26] Processors with non-multiple-of-four core counts have some cores disabled.
• Four ALUs, two AGUs/load–store units, and two floating-point units per core.^[27]
• Newly introduced "large" micro-operation cache.^[28]
• Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle).^[29][30]
• Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.
• Clock gating.
• Larger retire, load, and store queues.
• Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture,^[31] something that has been compared to a neural network by AMD engineer Mike Clark.^[32]
• The branch predictor is decoupled from the fetch stage.
• A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors.^[33]
• Move elimination, a method that reduces physical data movement to reduce power consumption.
• Binary compatibility with Intel's Skylake (excluding VT-x and private MSRs):
  • RDSEED support, a set of high-performance hardware random number generator instructions introduced in Broadwell.^[34]
  • Support for the SMAP, SMEP, XSAVEC/XSAVES/XRSTORS, and CLFLUSHOPT instructions.^[34]
  • ADX support.
  • SHA support.
• CLZERO instruction for clearing a cache line.^[34] Useful for handling ECC-related Machine-check exceptions.
• PTE (page table entry) coalescing, which combines 4 kB page tables into 32 kB page size.
• "Pure Power" (more accurate power monitoring sensors).^[35]
  • Support for intel-style running average power limit (RAPL) measurement.^[36]
• Smart Prefetch.
• Precision Boost.
• eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.^[37]

This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.

— Suzanne Plummer, Zen team leader, on September 19th, 2015.^[38]

The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries,^[39] which in turn licenses its 14 nm process from Samsung Electronics.^[40] This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.^[41] The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power).^[41] While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.^[42]

Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments.^[43][44] Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.^[45] There are also improvements in the branch predictor. The L1 cache size is 64 KB for instructions per core and 32 KB for data per core. The L2 cache size 512 KB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.

History and development

AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012.^[46] AMD formally revealed Zen in 2015.

The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.^[47][48] The Chief Architect of Zen was AMD Senior Fellow Michael Clark.^[49][50][51]

Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,^[9] with the release of the first Zen-based processors expected for October 2016.^[52]

In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".^[2][53]

In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture.^[54] This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.^[55] AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.

In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.^[56]

Advantages over predecessors

Manufacturing process

Processors based on Zen use 14 nm FinFET silicon.^[57] These processors are reportedly produced at GlobalFoundries.^[58] Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures.^[59][60] The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET;^[61] though Intel planned to begin the release of 10 nm parts later in 2017.^[62] Intel was unable to reach this goal, and in 2021, only mobile chips have been produced with the 10nm process. In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller.^[63] Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.^[64]

For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.^[65]

Performance

One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in instructions per cycle (IPC) over its predecessor.^[66] Excavator, in comparison, offered 4–15% improvement over previous architectures.^[67][68] AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.^[69] The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.

The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.^[70] This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.

AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in Blender rendering^[4][10] and HandBrake benchmarks.^[70]

Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one.^[71][72] This difference was corrected in Zen 2.

Memory

Zen supports DDR4 memory (up to eight channels)^[73] and ECC.^[74]

Pre-release reports stated APUs using the Zen architecture would also support High Bandwidth Memory (HBM).^[75] However, the first demonstrated APU did not use HBM.^[76] Previous APUs from AMD relied on shared memory for both the GPU and the CPU.

Power consumption and heat output

Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.

Zen also uses clock gating,^[44] reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.^[70]

Enhanced security and virtualization support

Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.^[77][78]

SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.^[79]

The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.^[80]

Connectivity

Incorporating much of the southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links.^[81][82] This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.^[83]

AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building deep learning systems.^[84][85] The 128^[86] PCIe lanes per Naples CPU allows for eight Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40^{[citation needed]} PCIe lanes.

Features

CPUs

APUs

APU features table

Products

The Zen architecture is used in the current-generation desktop Ryzen CPUs. It is also in Epyc server processors (successor of Opteron processors), and APUs.^{[75][unreliable source][87][88]}

The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codenamed "Raven Ridge") following in late 2017.^[89] AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.^[10]

In December 2016, AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.^[90]

On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous K15h (Piledriver) architecture.^[91][92] The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.^[93][94]

In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.^[4][10]

Desktop processors

Main article: Ryzen

Common features of Ryzen 1000 desktop CPUs:

• Socket: AM4.
• All the CPUs support DDR4-2666 in dual-channel mode.
• All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• Node/fabrication process: GlobalFoundries 14 LP.

Branding and Model		Cores (threads)	Clock rate (GHz)			L3 cache (total)	TDP	Core config[i]	Release date	Launch price[a]
			Base	PBO 1–2 (≥3)	XFR[95] 1–2
Ryzen 7	1800X[96]	8 (16)	3.6	4.0 (3.7)	4.1	16 MB	95 W	2 × 4	March 2, 2017	US $499
	PRO 1700X		3.4	3.8 (3.5)	3.9				June 29, 2017	OEM
	1700X[96]								March 2, 2017	US $399
	PRO 1700		3.0	3.7 (3.2)	3.75		65 W		June 29, 2017	OEM
	1700[96]								March 2, 2017	US $329
Ryzen 5	1600X[97]	6 (12)	3.6	4.0 (3.7)	4.1		95 W	2 × 3	April 11, 2017	US $249
	PRO 1600		3.2	3.6 (3.4)	3.7		65 W		June 29, 2017	OEM
	1600[97]								April 11, 2017	US $219
	1500X[97]	4 (8)	3.5	3.7 (3.6)	3.9			2 × 2		US $189
	PRO 1500								June 29, 2017	OEM
	1400[97]		3.2	3.4 (3.4)	3.45	8 MB			April 11, 2017	US $169
Ryzen 3	1300X[98]	4 (4)	3.5	3.7 (3.5)	3.9				July 27, 2017	US $129
	PRO 1300								June 29, 2017	OEM
	PRO 1200		3.1	3.4 (3.1)	3.45
	1200[98]								July 27, 2017	US $109

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1. Manufacturer suggested retail price at launch

1. Core Complexes (CCX) × cores per CCX

Common features of Ryzen 1000 HEDT CPUs:

• Socket: TR4.
• All the CPUs support DDR4-2666 in quad-channel mode.
• All the CPUs support 64 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• No integrated graphics.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• Node/fabrication process: GlobalFoundries 14LP.

Branding and Model		Cores (threads)	Clock rate (GHz)			L3 cache (total)	TDP	Chiplets	Core config[i]	Release date	Launch price[a]
			Base	PBO 1–4 (≥5)	XFR[95] 1–2
Ryzen Threadripper	1950X[99]	16 (32)	3.4	4.0 (3.7)	4.2	32 MB	180 W	2 × CCD[ii]	4 × 4	August 10, 2017	US $999
	1920X[99]	12 (24)	3.5						4 × 3		US $799
	1900X[99]	8 (16)	3.8	4.0 (3.9)		16 MB			2 × 4	August 31, 2017	US $549

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1. Manufacturer suggested retail price at launch

1. Core Complexes (CCX) × cores per CCX
2. Processor package actually contains two additional inactive dies to provide structural support to the integrated heat spreader.

Ryzen 5 1600 CPU on a motherboard

Threadripper 1950X TR4 in socket

Desktop APUs

Ryzen APUs are identified by either the G or GE suffix in their name.

Die shot of an AMD 2200G APU

Model	Release date & price	Fab	Thermal Solution	CPU						GPU				Socket	PCIe lanes	DDR4 memory support	TDP (W)
				Cores (threads)	Clock rate (GHz)		Cache			Model	Config[i]	Clock (GHz)	Processing power (GFLOPS)[ii]
					Base	Boost	L1	L2	L3
Athlon 200GE[100]	September 6, 2018 US $55	GloFo 14LP	AMD 65W thermal solution	2 (4)	3.2	—	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Vega 3	192:12:4 3 CU	1.0	384	AM4	16 (8+4+4)	2667 dual-channel	35
Athlon Pro 200GE[101]	September 6, 2018 OEM		OEM
Athlon 220GE[102]	December 21, 2018 US $65		AMD 65W thermal solution		3.4
Athlon 240GE[103]	December 21, 2018 US $75				3.5
Athlon 3000G[104]	November 19, 2019 US $49											1.1	424.4
Athlon 300GE[105]	July 7, 2019 OEM		OEM		3.4
Athlon Silver 3050GE[106]	July 21, 2020 OEM
Ryzen 3 Pro 2100GE[107]	c. 2019 OEM				3.2	?							?			2933 dual-channel
Ryzen 3 2200GE[108]	April 19, 2018 OEM			4 (4)	3.2	3.6				Vega 8	512:32:16 8 CU		1126
Ryzen 3 Pro 2200GE[109]	May 10, 2018 OEM
Ryzen 3 2200G	February 12, 2018 US $99		Wraith Stealth		3.5	3.7											45– 65
Ryzen 3 Pro 2200G[110]	May 10, 2018 OEM		OEM
Ryzen 5 2400GE[111]	April 19, 2018 OEM			4 (8)	3.2	3.8				RX Vega 11	704:44:16 11 CU	1.25	1760				35
Ryzen 5 Pro 2400GE[112]	May 10, 2018 OEM
Ryzen 5 2400G[113]	February 12, 2018[114][115] US $169		Wraith Stealth		3.6	3.9											45– 65
Ryzen 5 Pro 2400G[116]	May 10, 2018 OEM		OEM

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1. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Mobile APUs

Model	Release date	Fab	CPU						GPU				Socket	PCIe lanes	Memory support	TDP
			Cores (threads)	Clock rate (GHz)		Cache			Model	Config[i]	Clock (MHz)	Processing power (GFLOPS)[ii]
				Base	Boost	L1	L2	L3
Athlon Pro 200U	2019	GloFo 14LP	2 (4)	2.3	3.2	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Radeon Vega 3	192:12:4 3 CU	1000	384	FP5	12 (8+4)	DDR4-2400 dual-channel	12–25 W
Athlon 300U	Jan 6, 2019			2.4	3.3
Ryzen 3 2200U	Jan 8, 2018			2.5	3.4						1100	422.4
Ryzen 3 3200U	Jan 6, 2019			2.6	3.5						1200	460.8
Ryzen 3 2300U	Jan 8, 2018		4 (4)	2.0	3.4				Radeon Vega 6	384:24:8 6 CU	1100	844.8
Ryzen 3 Pro 2300U	May 15, 2018
Ryzen 5 2500U	Oct 26, 2017		4 (8)		3.6				Radeon Vega 8	512:32:16 8 CU		1126.4
Ryzen 5 Pro 2500U	May 15, 2018
Ryzen 5 2600H	Sep 10, 2018			3.2											DDR4-3200 dual-channel	35–54 W
Ryzen 7 2700U	Oct 26, 2017			2.2	3.8				Radeon RX Vega 10	640:40:16 10 CU	1300	1664			DDR4-2400 dual-channel	12–25 W
Ryzen 7 Pro 2700U	May 15, 2018								Radeon Vega 10
Ryzen 7 2800H	Sep 10, 2018			3.3					Radeon RX Vega 11	704:44:16 11 CU		1830.4			DDR4-3200 dual-channel	35–54 W

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1. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
2. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Ultra-mobile APUs

Dalí

Model	Release date	Fab	CPU						GPU				Socket	PCIe lanes	Memory support	TDP	Part number
			Cores (threads)	Clock rate (GHz)		Cache			Model	Config[a]	Clock (GHz)	Processing power (GFLOPS)[b]
				Base	Boost	L1	L2	L3
AMD 3020e	Jan 6, 2020	14 nm	2 (2)	1.2	2.6	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Radeon Graphics (Vega)	192:12:4 3 CU	1.0	384	FP5	12 (8+4)	DDR4-2400 dual-channel	6 W	YM3020C7T2OFG
Athlon PRO 3045B	Q1 2021			2.3	3.2					128:8:4 2 CU	1.1	281.6				15 W	YM3045C4T2OFG
Athlon Silver 3050U	Jan 6, 2020																YM3050C4T2OFG
Athlon Silver 3050C	Sep 22, 2020																YM305CC4T2OFG
Athlon Silver 3050e	Jan 6, 2020		2 (4)	1.4	2.8					192:12:4 3 CU[117]	1.0	384				6 W	YM3050C7T2OFG
Athlon PRO 3145B	Q1 2021			2.4	3.3											15 W	YM3145C4T2OFG
Athlon Gold 3150U	Jan 6, 2020																YM3150C4T2OFG
Athlon Gold 3150C	Sep 22, 2020																YM315CC4T2OFG
Ryzen 3 3250U	Jan 6, 2020			2.6	3.5						1.2	460.8					YM3250C4T2OFG
Ryzen 3 3250C	Sep 22, 2020																YM325CC4T2OFG

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1. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
2. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Pollock

Model	Release date	Fab	CPU						GPU				Socket	PCIe lanes	Memory support	TDP	Part number
			Cores (threads)	Clock rate (GHz)		Cache			Model	Config[a]	Clock (GHz)	Processing power (GFLOPS)[b]
				Base	Boost	L1	L2	L3
AMD 3015e	Jul 6, 2020	14 nm	2 (4)	1.2	2.3	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Radeon Graphics (Vega)	192:12:4 3 CU	0.6	230.4	FT5	12 (8+4)	DDR4-1600 single-channel	6 W	AM3015BRP2OFJ
AMD 3015Ce	Apr 29, 2021																AM301CBRP2OFJ

• v
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1. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
2. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Embedded processors

V1000

In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.^[118] (And three more SKUs in December that year.)

Model	Release date	Fab	CPU						GPU				Memory support	TDP	Junction temp. range (°C)
			Cores (threads)	Clock rate (GHz)		Cache			Model	Config[i]	Clock (GHz)	Processing power (GFLOPS)[ii]
				Base	Boost	L1	L2	L3
V1202B	February 2018	GloFo 14LP	2 (4)	2.3	3.2	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Vega 3	192:12:16 3 CU	1.0	384	DDR4-2400 dual-channel	12–25 W	0–105
V1404I	December 2018		4 (8)	2.0	3.6				Vega 8	512:32:16 8 CU	1.1	1126.4			-40–105
V1500B				2.2	—				—						0–105
V1605B	February 2018			2.0	3.6				Vega 8	512:32:16 8 CU	1.1	1126.4
V1756B				3.25									DDR4-3200 dual-channel	35–54 W
V1780B	December 2018			3.35					—
V1807B	February 2018				3.8				Vega 11	704:44:16 11 CU	1.3	1830.4

• v
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1. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

R1000

In 2019, AMD announced the R1000 series of embedded Zen+Vega APUs.

Model	Release date	Fab	CPU						GPU				Memory support	TDP
			Cores (threads)	Clock rate (GHz)		Cache			Model	Config[i]	Clock (GHz)	Processing power (GFLOPS)[ii]
				Base	Boost	L1	L2	L3
R1102G	February 25, 2020	GloFo 14LP	2 (2)	1.2	2.6	64 KB inst. 32 KB data per core	512 KB per core	4 MB	Vega 3	192:12:4 3 CU	1.0	384	DDR4-2400 single-channel	6 W
R1305G			2 (4)	1.5	2.8								DDR4-2400 dual-channel	8-10 W
R1505G	April 16, 2019			2.4	3.3									12–25 W
R1606G				2.6	3.5						1.2	460.8

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1. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Server processors

Main article: Epyc

Epyc

AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric.^[119] Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.^[120] AMD officially revealed Naples under the brand name Epyc in May 2017.^[121]

On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.^[122] Common features:

• SP3 socket
• Zen microarchitecture
• GloFo 14 nm process
• MCM with four System-on-a-chip (SOC) dies, two core complexes (CCX) per SOC die^[123]
• Eight-channel DDR4-2666 (the 7251 model is limited to DDR4-2400)
• 128 PCIe 3.0 lanes per socket, 64 of which are used for Infinity Fabric inter-processor links in 2P platforms
• 7001P series models are limited to uniprocessor operation (1P)

Model	Cores (threads)	Chiplets	Core config[i]	Clock rate		Cache size			Socket	Scaling	TDP	Release date	Release price	Embedded options[ii]
				Base (GHz)	Boost (GHz)	L2 per core	L3 per CCX	Total
7251[124][125]	8 (16)	4[123]	8 × 1	2.1	2.9	512 KB	4 MB	36 MB	SP3	2P	120 W	Jun 2017[126]	$475	7251
7261[124][127]				2.5	2.9		8 MB	68 MB		2P	155/170 W	Jun 2018[128]	$570	7261
7281[124][125]	16 (32)		8 × 2	2.1	2.7		4 MB	40 MB		2P	155/170 W	Jun 2017[126]	$650	7281
7301[124][125]				2.2	2.7		8 MB	72 MB		2P			$800	7301
7351(P)[124][125]				2.4	2.9					2P (1P)			$1100 ($750)	7351(735P)
7371[124][129]				3.1	3.8					2P	200 W	Nov 2018[130]	$1550	7371
7401(P)[124][125]	24 (48)		8 × 3	2.0	3.0		8 MB	76 MB		2P (1P)	155/170 W	Jun 2017[126]	$1850 ($1075)	7401(740P)
7451[124][125]				2.3	3.2					2P	180 W		$2400	7451
7501[124][125]	32 (64)		8 × 4	2.0	3.0		8 MB	80 MB		2P	155/170 W	Jun 2017[126]	$3400	7501
7551(P)[124][125]				2.0	3.0					2P (1P)	180 W		$3400 ($2100)	7551(755P)
7571[131][132]				2.2	3.0					2P	200 W	Nov 2018	OEM/AWS	--
7601[124][125]				2.2	3.2					2P	180 W	Jun 2017[126]	$4200	7601

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1. Core Complexes (CCX) × cores per CCX
2. Epyc Embedded 7001 series models have identical specifications as the respective Epyc 7001 series.

Embedded server processors

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.^[133]Common features of EPYC Embedded 3000 series CPUs:

• Socket: SP4 (31xx and 32xx models use SP4r2 package).
• All the CPUs support ECC DDR4-2666 in dual-channel mode (3201 supports only DDR4-2133), while 33xx and 34xx models support quad-channel mode.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 32 PCIe 3.0 lanes per CCD (max 64 lanes).
• Fabrication process: GlobalFoundries 14 nm.

Model	Cores (threads)	Clock rate (GHz)			L3 cache (total)	TDP	Chiplets	Core config[i]	Release date
		Base	Boost
			All-core	Max
3101[134]	4 (4)	2.1	2.9	2.9	8 MB	35 W	1 × CCD	1 × 4	Feb 2018
3151[134]	4 (8)	2.7			16 MB	45 W		2 × 2
3201[134]	8 (8)	1.5	3.1	3.1		30 W		2 × 4
3251[134]	8 (16)	2.5				55 W
3255[135]						25–55 W			Dec 2018
3301[134]	12 (12)	2.0	2.15	3.0	32 MB	65 W	2 × CCD	4 × 3	Feb 2018
3351[134]	12 (24)	1.9	2.75			60–80 W
3401[134]	16 (16)	1.85	2.25			85 W		4 × 4
3451[134]	16 (32)	2.15	2.45			80–100 W

• v
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1. Core Complexes (CCX) × cores per CCX

See also

• AMD K9
• AMD K10
• Jim Keller (engineer)
• Ryzen
• Steamroller (microarchitecture)
• Zen+
• Zen 2