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Computer memory chips used as a set From Wikipedia, the free encyclopedia
A memory rank is a set of DRAM chips connected to the same chip select, which are therefore accessed simultaneously. In practice all DRAM chips share all of the other command and control signals, and only the chip select pins for each rank are separate (the data pins are shared across ranks).[1]
The term rank was created and defined by JEDEC, the memory industry standards group. On a DDR, DDR2, or DDR3 memory module, each rank has a 64-bit-wide data bus (72 bits wide on DIMMs that support ECC). The number of physical DRAMs depends on their individual widths. For example, a rank of ×8 (8-bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of ×4 (4-bit wide) DRAMs would consist of 16 physical chips (18, if ECC is supported). Multiple ranks can coexist on a single DIMM. Modern DIMMs can for example feature one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).[citation needed]
There is only a little difference between a dual rank UDIMM and two single-rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs. The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increase the memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. Also some memory controllers have a maximum supported number of ranks. DRAM load on the command/address (CA) bus can be reduced by using registered memory.[citation needed]
Predating the term rank (sometimes also called row) is the use of single-sided and double-sided modules, especially with SIMMs. While most often the number of sides used to carry RAM chips corresponded to the number of ranks, sometimes they did not. This could lead to confusion and technical issues.[2][3]
A Multi-Ranked Buffered DIMM (MR-DIMM) allows both ranks to be accessed simultaneously by the memory controller, and is supported by AMD, Google, Microsoft, JEDEC, and Intel.[4]
There are several effects to consider regarding memory performance in multi-rank configurations:
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