Verilog-AMS是Verilog硬件描述語言的一個衍生。它包含了模擬和混合信號擴展模塊,以實現對於模擬電路和混合信號系統行為的描述。它擴展了Verilog、SystemVerilog等的事件驅動仿真器的迴路,通過使用一個連續時間仿真器,可以在模擬域(analog-domain)上求解微分方程。模擬事件可以觸發數字行為,反之亦可。[1]
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