VIA Nano

"VIA CN" redirects here. "VIA CN" can also mean that VIA Rail uses CN trackage.

The VIA Nano (formerly code-named VIA Isaiah) is a 64-bit CPU for personal computers. The VIA Nano was released by VIA Technologies in 2008 after five years of development^[1] by its CPU division, Centaur Technology. This Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008,^[2][3][4][5] and launched on 29 May, including low-voltage variants and the Nano brand name.^[6] The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.

VIA Nano

General information
Marketed by	VIA Technologies
Designed by	Centaur Technology
Common manufacturers	Fujitsu TSMC
Performance
FSB speeds	533 MHz to 1066 MHz
Cache
L1 cache	64 KiB instruction + 64 KiB data per core
L2 cache	1 MiB per core, exclusive
Architecture and classification
Technology node	40 nm to 65 nm
Microarchitecture	VIA Isaiah
Instruction set	IA-32, x86-64
Extensions	MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 (3000, X2, QuadCore), SSE4.2 (C), PadLock (AES, RNG, SHA)
Physical specifications
Cores	1, 2, 4
Package	Ball grid array (soldered)
Products, models, variants
Core name	Isaiah (CN)
History
Predecessor	VIA C7

VIA Nano 2 Logo

History

Unlike Intel and AMD, VIA uses two distinct development code names for each of its CPU cores. In this case, the codename 'CN' was used in the United States by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah was the choice for this particular processor and architecture. It is expected that the VIA Isaiah will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W.^[7] Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line, while retaining their encryption extensions. Several independent tests showed that the VIA Nano performs better than the single-core Intel Atom across a variety of workloads.^[8][9][10] In a 2008 Ars Technica test, a VIA Nano gained significant performance in memory subsystem after its CPUID changed to Intel, hinting at the possibility that the benchmark software only checks the CPUID instead of the actual features supported by the CPU to choose a code path. The benchmark software used had been released before the release of VIA Nano.^[11]

On November 3, 2009, VIA launched the Nano 3000 series. VIA claims that these models can offer a 20% performance boost and 20% more energy efficiency than the Nano 1000 and 2000 series.^[12] Benchmarks run by VIA claim that a 1.6 GHz 3000-series Nano can outperform the ageing Intel Atom N270 by about 40–54%.^[13] The 3000 series adds the SSE4 SIMD instruction set extensions, which were first introduced with 45 nm revisions of the Intel Core 2 architecture.

On November 11, 2011, VIA released the VIA Nano X2 Dual-Core Processor with their first ever dual core pico-itx mainboard. The VIA Nano X2 is built on a 40 nm process and supports the SSE4 SIMD instruction set extensions, critical to modern floating point dependent applications.^[14] Via claims 30% higher performance in comparison to Intel's Atom with a 50% higher clock.^[15]

The Zhaoxin joint venture processors, released from 2014, are based on the VIA Nano series.

Features

VIA Isaiah floorplan

• x86-64 instruction set
• Clock speed from 1 GHz to 2 GHz
• Bus speed of 533 MHz or 800 MHz (1066 MHz for Nano x2)
• 64 KB data and 64 KB instructions L1 cache and 1 MB L2 cache per core.^[16]
• 65 nm manufacturing process (40 nm for Nano x2)
• Superscalar out-of-order instruction execution
• Support for MMX, SSE, SSE2, SSE3, SSSE3, and SSE4 instruction set
• Support for x86 virtualization with Intel-compatible implementation (disabled before stepping 3)
• Support for ECC memory
• Pin-compatible with VIA C7 and VIA Eden

Architecture overview

VIA Isaiah Architecture die floor-plan

Nano X2 microarchitecture.

• Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with same year offerings from AMD and Intel.
• Instructions fusion: Allows the processor to combine multiple instructions into a single one, improving performance and reducing power consumption. This technique, similar to the approach used by the Atom processor, is more efficient than breaking down instructions into smaller units.
• Improved branch prediction: Uses eight predictors in two pipeline stages.
• CPU cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
• Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
  • Fetches four x86 instructions per cycle as opposed to Intel's three to five cycles.
  • Issues three micro-operations/clock to execution units
• Memory access: Merges smaller stores into larger load data.
• Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
  • Two integer units (ALU1 and ALU2)
    • ALU1 is feature complete, while ALU2 lacks some low usage instructions and therefore is more suited for tasks like address calculations.
  • Two store units, one for Address Store and one for Data Store according to VIA.
  • One load unit
  • Two media units (MEDIA-A and MEDIA-B) with a 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations. Media computation refers to the use of the two media units.
    • MEDIA-A executes floating-point "add" instructions (2-clock latency for single-precision and double-precision), integer SIMD, encryption, divide and square root.
    • MEDIA-B executes floating-point "multiply" instructions (2-clock latency for single-precision, 3-clock latency for double-precision).
    • Because of the parallelism introduced with the two media units, media computation can provide four "add" and four "multiply" instructions per clock.
  • A new implementation of FP-addition with the lowest clock-latency for a x86 processor so far.
  • Almost all integer SIMD instructions execute in one clock.
  • Implements MMX, SSE, SSE2, SSE3, SSSE3 multimedia instruction sets
  • Implements SSE4.1 multimedia instruction set (VIA Nano 3000 series)
  • Implements SSE4.1 multimedia instruction set (VIA Nano x2 series)
• Power Management: Besides requiring very low power, many new features are included.
  • Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
  • Adaptive P-State Control: Transition between performance and voltage states without stopping execution.
  • Adaptive Overclocking: Automatic overclocking if there is low temperature in the processor core.
  • Adaptive Thermal Limit: Adjusting of the processor to maintain a user predefined temperature.
• Encryption: Includes the VIA PadLock engine
  • Hardware support for AES encryption, secure hash algorithm SHA-1 and SHA-256 and Random Number Generation

See also

• List of VIA Nano microprocessors
• List of VIA microprocessors
• Netbook