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For other uses, see SPARC (disambiguation).

SPARC (Scalable Processor ARChitecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems.[1][2] Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987,[3][2] SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s.

Quick Facts Designer, Bits ...
SPARC
Thumb
DesignerSun Microsystems (acquired by Oracle Corporation)[1][2]
Bits64-bit (32 → 64)
Introduced1986; 38 years ago (1986) (production)
1987; 37 years ago (1987) (shipments)
VersionV9 (1993) / OSA2017
DesignRISC
TypeLoad–store
EncodingFixed
BranchingCondition code
EndiannessBi (Big → Bi)
Page size8 KB (4 KB → 8 KB)
ExtensionsVIS 1.0, 2.0, 3.0, 4.0
OpenYes, and royalty free
Registers
General-purpose31 (G0 = 0; non-global registers use register windows)
Floating point32 (usable as 32 single-precision, 32 double-precision, or 16 quad-precision)
Close
Thumb
A Sun UltraSPARC II microprocessor (1997)

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne, and Fujitsu, among others.

The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments. Due to SPARC International, SPARC is fully open, non-proprietary and royalty-free.

As of 2024, the latest commercial high-end SPARC processors are Fujitsu's SPARC64 XII (introduced in September 2017 for its SPARC M12 server) and Oracle's SPARC M8 introduced in September 2017 for its high-end servers.

On September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing the M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts.[4][5]

Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM-based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and a year later for their mainframe and end-of-support in 2034 "to promote customer modernization".[6]

Features

The SPARC architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 160 general-purpose registers. According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers.[7] At any point, only 32 of them are immediately visible to software — 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has eight local registers and shares eight registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls.

The "scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The architecture has gone through several revisions. It gained hardware multiply and divide functionality in version 8.[8][9] 64-bit (addressing and data) were added to the version 9 SPARC specification published in 1994.[10]

In SPARC version 8, the floating-point register file has 16 double-precision registers. Each of them can be used as two single-precision registers, providing a total of 32 single-precision registers. An odd–even number pair of double-precision registers can be used as a quad-precision register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2024.[11]

Tagged add and subtract instructions perform adds and subtracts on values checking that the bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load–store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses.

History

There have been three major revisions of the architecture. The first published version was the 32-bit SPARC version 7 (V7) in 1986. SPARC version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit "quad-precision" arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.

SPARC version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments. Newer specifications always remain compliant with the full SPARC V9 Level 1 specification.

In 2002, the SPARC Joint Programming Specification 1 (JPS1) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements".

At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were the UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu.

In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, and IV+, as well as CMT extensions starting with the UltraSPARC T1 implementation:

  • the VIS 1 and VIS 2 instruction set extensions and the associated GSR register
  • multiple levels of global registers, controlled by the GL register
  • Sun's 64-bit MMU architecture
  • privileged instructions ALLCLEAN, OTHERW, NORMALW, and INVALW
  • access to the VER register is now hyperprivileged
  • the SIR instruction is now hyperprivileged

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

In December 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project.[12] It was also released under the GNU General public license v2.[13] OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads.

In August 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification.[14]

In October 2015, Oracle released SPARC M7, the first processor based on the new Oracle SPARC Architecture 2015 specification.[7][15] This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM).[16]

SPARC architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark.

Architecture

SPARC is a load–store architecture (also known as a register–register architecture); except for the load/store instructions used to access memory, all instructions operate on the registers, in accordance with the RISC design principles.

A SPARC processor includes an integer unit (IU) that performs integer load, store, and arithmetic operations.[17]: 9 [10]: 15–16  It may include a floating-point unit (FPU) that performs floating-point operations[17]: 9 [10]: 15–16  and, for SPARC V8, may include a co-processor (CP) that performs co-processor-specific operations; the architecture does not specify what functions a co-processor would perform, other than load and store operations.[17]: 9 

Registers

The SPARC architecture has an overlapping register window scheme. At any instant, 32 general-purpose registers are visible. A Current Window Pointer (CWP) variable in the hardware points to the current set. The total size of the register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as CWP is 5 bits and is part of the PSR register.

In SPARC V7 and V8 CWP will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by the RESTORE instruction (switching back to the call before returning from the procedure). Trap events (interrupts, exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the CWP. For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions.

More information Register group, Mnemonic ...
Window Addressing
Register groupMnemonicRegister addressAvailability
globalG0...G7R[00]...R[07]always the same ones, G0 being zero always
outO0...O7R[08]...R[15]to be handed over to, and returned from, the called subroutine, as its "in"
localL0...L7R[16]...R[23]truly local to the current subroutine
inI0...I7R[24]...R[31]handed over from the caller, and returned to the caller, as its "out"
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SPARC registers are shown in the figure above.

There is also a non-windowed Y register, used by the multiply-step, integer multiply, and integer divide instructions.[17]: 32 

A SPARC V8 processor with an FPU includes 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number. An even–odd pair of floating-point registers can hold one double-precision IEEE 754 floating-point number, and a quad-aligned group of four floating-point registers can hold one quad-precision IEEE 754 floating-point number.[17]: 10 

A SPARC V9 processor with an FPU includes:[10]: 36–40 

  • 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number;
  • 32 64-bit floating-point registers, each of which can hold one double-precision IEEE 754 floating-point number;
  • 16 128-bit floating-point registers, each of which can hold one quad-precision IEEE 754 floating-point number.

The registers are organized as a set of 64 32-bit registers, with the first 32 being used as the 32-bit floating-point registers, even–odd pairs of all 64 registers being used as the 64-bit floating-point registers, and quad-aligned groups of four floating-point registers being used as the 128-bit floating-point registers.

Floating-point registers are not windowed; they are all global registers.[10]: 36–40 

Instruction formats

All SPARC instructions occupy a full 32-bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand.[18] RD is the "destination register", where the output of the operation is deposited. The majority of SPARC instructions have at least this register, so it is placed near the "front" of the instruction format. RS1 and RS2 are the "source registers", which may or may not be present, or replaced by a constant.

More information Type, Bit ...
SPARC instruction formats
Type Bit
313029282726252423222120191817161514131211109876543210
SETHI format00RD100Immediate constant 22 bits
I Branch format00Aicc010Displacement constant 22 bits
F Branch format00Afcc110Displacement constant 22 bits
C Branch format00Accc111Displacement constant 22 bits
CALL disp01PC-relative displacement
Arithmetic register10RDopcodeRS100RS2
Arithmetic immediate10RDopcodeRS11Immediate constant 13 bits
FPU operation10FD110100/110101FS1opfFS2
CP operation10RD110110/110111RS1opcRS2
JMPL register10RD111000RS100RS2
JMPL immediate10RD111000RS11Immediate constant 13 bits
LD/ST register11RDopcodeRS100RS2
LD/ST immediate11RDopcodeRS11Immediate constant 13 bits
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Instructions

Loads and stores

Load and store instructions have a three-operand format, in that they have two operands representing values for the address and one operand for the register to read or write to. The address is created by adding the two address operands to produce an address. The second address operand may be a constant or a register. Loads take the value at the address and place it in the register specified by the third operand, whereas stores take the value in the register specified by the first operand and place it at the address. To make this more obvious, the assembler language indicates address operands using square brackets with a plus sign separating the operands, instead of using a comma-separated list. Examples:[18]

ld [%L1+%L2],%L3  !load the 32-bit value at address %L1+%L2 and put the value into %L3
ld [%L1+8],%L2    !load the value at %L1+8 into %L2
ld [%L1],%L2      !as above, but no offset, which is the same as +%G0
st %L1,[%I2]      !store the value in %L1 into the location stored in %I2
st %G0,[%I1+8]    !clear the memory at %I1+8

Due to the widespread use of non-32-bit data, such as 16-bit or 8-bit integral data or 8-bit bytes in strings, there are instructions that load and store 16-bit half-words and 8-bit bytes, as well as instructions that load 32-bit words. During a load, those instructions will read only the byte or half-word at the indicated location and then either fill the rest of the target register with zeros (unsigned load) or with the value of the uppermost bit of the byte or half-word (signed load). During a store, those instructions discard the upper bits in the register and store only the lower bits. There are also instructions for loading double-precision values used for floating-point arithmetic, reading or writing eight bytes from the indicated register and the "next" one, so if the destination of a load is L1, L1 and L2 will be set. The complete list of load and store instructions for the general-purpose registers in 32-bit SPARC is LD, ST, LDUB (unsigned byte), LDSB (signed byte), LDUH (unsigned half-word), LDSH (signed half-word), LDD (load double), STB (store byte), STH (store half-word), STD (store double).[18]

In SPARC V9, registers are 64-bit, and the LD instruction, renamed LDUW, clears the upper 32 bits in the register and loads the 32-bit value into the lower 32 bits, and the ST instruction, renamed STW, discards the upper 32 bits of the register and stores only the lower 32 bits. The new LDSW instruction sets the upper bits in the register to the value of the uppermost bit of the word and loads the 32-bit value into the lower bits. The new LDX instruction loads a 64-bit value into the register, and the STX instruction stores all 64 bits of the register.

The LDF, LDDF, and LDQF instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the STF, STDF, and STQF instructions store a single-precision, double-precision, or quad-precision floating-point register into memory.

The memory barrier instruction, MEMBAR, serves two interrelated purposes: it articulates order constraints among memory references and facilitates explicit control over the completion of memory references. For example, all effects of the stores that appear prior to the MEMBAR instruction must be made visible to all processors before any loads following the MEMBAR can be executed.[19]

ALU operations

Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result. The middle operand can be a register or a 13-bit signed integer constant; the other operands are registers. Any of the register operands may point to G0; pointing the result to G0 discards the results, which can be used for tests. Examples include:[18]

add %L1,%L2,%L3   !add the values in %L1 and %L2 and put the result in %L3
add %L1,1,%L1     !increment %L1
add %G0,%G0,%L4   !clear any value in %L4

The list of mathematical instructions is ADD, SUB, AND, OR, XOR, and negated versions ANDN, ORN, and XNOR. One quirk of the SPARC design is that most arithmetic instructions come in pairs, with one version setting the NZVC condition code bits in the status register, and the other not setting them, with the default being not to set the codes. This is so that the compiler has a way to move instructions around when trying to fill delay slots. If one wants the condition codes to be set, this is indicated by adding cc to the instruction:[18]

subcc %L1,10,%G0  !compare %L1 to 10 and ignore the result, but set the flags

add and sub also have another modifier, X, which indicates whether the operation should set the carry bit:

addx %L1,100,%L1  !add 100 to the value in %L1 and track carry

SPARC V7 does not have multiplication or division instructions, but it does have MULSCC, which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy. SPARC V8 added UMUL (unsigned multiply), SMUL (signed multiply), UDIV (unsigned divide), and SDIV (signed divide) instructions, with both versions that do not update the condition codes and versions that do. MULSCC and the multiply instructions use the Y register to hold the upper 32 bits of the product; the divide instructions use it to hold the upper 32 bits of the dividend. The RDY instruction reads the value of the Y register into a general-purpose register; the WRY instruction writes the value of a general-purpose register to the Y register.[17]: 32  SPARC V9 added MULX, which multiplies two 64-bit values and produces a 64-bit result, SDIVX, which divides a 64-bit signed dividend by a 64-bit signed divisor and produces a 64-bit signed quotient, and UDIVX, which divides a 64-bit unsigned dividend by a 64-bit unsigned divisor and produces a 64-bit signed quotient; none of those instructions use the Y register.[10]: 199 

Branching

Conditional branches test condition codes in a status register, as seen in many instruction sets such the IBM System/360 architecture and successors and the x86 architecture. This means that a test and branch is normally performed with two instructions; the first is an ALU instruction that sets the condition codes, followed by a branch instruction that examines one of those flags. The SPARC does not have specialized test instructions; tests are performed using normal ALU instructions with the destination set to %G0. For instance, to test if a register holds the value 10 and then branch to code that handles it, one would:

subcc %L1,10,%G0 !subtract 10 from %L1, setting the zero flag if %L1 is 10
be WASEQUAL      !if the zero flag is set, branch to the address marked WASEQUAL

In a conditional branch instruction, the icc or fcc field specifies the condition being tested. The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes. The ANNUL (A) bit is used to get rid of some delay slots. If it is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped.

There are a wide variety of conditional branches: BA (branch always, essentially a jmp), BN (branch never), BE (equals), BNE (not equals), BL (less than), BLE (less or equal), BLEU (less or equal, unsigned), BG (greater), BGE (greater or equal), BGU (greater unsigned), BPOS (positive), BNEG (negative), BCC (carry clear), BCS (carry set), BVC (overflow clear), BVS (overflow set).[17]: 119–120 

The FPU and CP have sets of condition codes separate from the integer condition codes and from each other; two additional sets of branch instructions were defined to test those condition codes. Adding an F to the front of the branch instruction in the list above performs the test against the FPU's condition codes,[17]: 121–122  while, in SPARC V8, adding a C tests the flags in the otherwise undefined CP.[17]: 123–124 

The CALL (jump to subroutine) instruction uses a 30-bit program counter-relative word offset. As the target address is specifying the start of a word, not a byte, 30-bits is all that is needed to reach any address in the 4 gigabyte address space.[18] The CALL instruction deposits the return address in register R15, also known as output register O7.

The JMPL (jump and link) instruction is a three-operand instruction, with two operands representing values for the target address and one operand for a register in which to deposit the return address. The address is created by adding the two address operands to produce a 32-bit address. The second address operand may be a constant or a register.

Large constants

As the instruction opcode takes up some bits of the 32-bit instruction word, there is no way to load a 32-bit constant using a single instruction. This is significant because addresses are manipulated through registers and they are 32-bits. To ease this, the special-purpose SETHI instruction copies its 22-bit immediate operand into the high-order 22 bits of any specified register, and sets each of the low-order 10 bits to 0. In general use, SETHI is followed by an or instruction with only the lower 10 bits of the value set. To ease this, the assembler includes the %hi(X) and %lo(X) macros. For example:[18]

sethi %hi(0x89ABCDEF),%L1       !sets the upper 22 bits of L1
or    %L1,%lo(0x89ABCDEF),%L1   !sets the lower 10 bits of L1 by ORing

The hi and lo macros are performed at assembly time, not runtime, so it has no performance hit yet makes it clearer that L1 is set to a single value, not two unrelated ones. To make this even easier, the assembler also includes a "synthetic instruction", set, that performs these two operations in a single line:

set   0x89ABCDEF,% L1

This outputs the two instructions above if the value is larger than 13 bits, otherwise it will emit a single ld with the value.[18]

Synthetic instructions

As noted earlier, the SPARC assembler uses "synthetic instructions" to ease common coding tasks. Additional examples include (among others):[18]

More information mnemonic, actual output ...
SPARC synthetic instructions
mnemonic actual output purpose
nopsethi 0,%g0do nothing
clr %regor %g0,%g0,%regset a register to zero
clr [address]st %g0,[address]set a memory address to zero
clrh [address]sth %g0,[address]set the half-word at memory address to zero
clrb [address]stb %g0,[address]set the byte at memory address to zero
cmp %reg1,%reg2subcc %reg1,%reg2,%g0compare two registers, set codes, discard results
cmp %reg,constsubcc %reg,const,%g0compare register with constant
mov %reg1,%reg2or %g0,%reg1,%reg2copy value from one register to another
mov const,%regor %g0,const,%regcopy constant value into a register
inc %regadd %reg,1,%regincrement a register
inccc %regaddcc %reg,1,%regincrement a register, set conditions
dec %regsub %reg,1,%regdecrement a register
deccc %regsubcc %reg,1,%regdecrement a register, set conditions
not %regxnor %reg,%g0,%regflip the bits in a register
neg %regsub %g0,%reg,%regtwo's complement a register
tst %regorcc %reg,%g0,%g0test whether the value in a register is > 0, 0, or < 0
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SPARC architecture licensees

Intel was the 80386's only producer, which made it very expensive and caused the industry to be wary of sole sourced CPUs. When Sun announced SPARC in 1987, the company stated that it would be available from multiple sources. Fujitsu was the first SPARC vendor, and Cypress Semiconductor was the second licensee; as of February 1989 their SPARC CPUs were available, as was Texas Instruments's FPU.[20] The following organizations have licensed the SPARC architecture:

Implementations

More information Name (codename), Model ...
Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)
SPARC MB86900 Fujitsu[1][3][2] 14.28–33V719861×1=113000.11—256——0–128 (unified)nonenone
SPARC Various[note 2] 14.28–40V71989–19921×1=1800–1300~0.1–1.8—160–256——0–128 (unified)nonenone
MN10501 (KAP) Solbourne Computer,

Matsushita[21]

 33–36 V8 1990–1991 1x1=1 — 1.0[22] — — — — 8 8 0–256 none
microSPARC I (Tsunami) TI TMS390S10 40–50V819921×1=18000.8225?2882.5524nonenone
SuperSPARC I (Viking) TI TMX390Z50 / Sun STP1020 33–60V819921×1=18003.1—29314.3516200–2048none
SPARClite Fujitsu MB8683x 66–108V8E19921×1=1———144, 176—2.5/3.3–5.0 V, 2.5–3.3 V1, 2, 8, 161, 2, 8, 16nonenone
hyperSPARC (Colorado 1) Ross RT620A 40–90V819931×1=15001.5———5?08128–256none
microSPARC II (Swift) Fujitsu MB86904 / Sun STP1012 60–125V819941×1=15002.323332153.3816nonenone
hyperSPARC (Colorado 2) Ross RT620B 90–125V819941×1=14001.5———3.308128–256none
SuperSPARC II (Voyager) Sun STP1021 75–90V819941×1=18003.1299—16—16201024–2048none
hyperSPARC (Colorado 3) Ross RT620C 125–166V819951×1=13501.5———3.308512–1024none
TurboSPARC Fujitsu MB86907 160–180V819961×1=13503.013241673.51616512none
UltraSPARC (Spitfire) Sun STP1030 143–167V919951×1=14703.831552130[note 3]3.31616512–1024none
UltraSPARC (Hornet) Sun STP1030 200V919951×1=14205.2265521—3.31616512–1024none
hyperSPARC (Colorado 4) Ross RT620D 180–200V819961×1=13501.7———3.31616512none
SPARC64 Fujitsu (HAL) 101–118V919951×1=1400—Multichip286503.8128128——
SPARC64 II Fujitsu (HAL) 141–161V919961×1=1350—Multichip286643.3128128——
SPARC64 III Fujitsu (HAL) MBCS70301 250–330V919981×1=124017.6240——2.564648192—
UltraSPARC IIs (Blackbird) Sun STP1031 250–400V919971×1=13505.414952125[note 4]2.516161024 or 4096none
UltraSPARC IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480V919991×1=12505.412652121[note 5]1.916161024–8192none
UltraSPARC IIi (Sabre) Sun SME1040 270–360V919971×1=13505.4156587211.91616256–2048none
UltraSPARC IIi (Sapphire-Red) Sun SME1430 333–480V919981×1=12505.4—58721[note 6]1.916162048none
UltraSPARC IIe (Hummingbird) Sun SME1701 400–500V919991×1=1180 Al——37013[note 7]1.5–1.71616256none
UltraSPARC IIi (IIe+) (Phantom) Sun SME1532 550–650V920001×1=1180 Cu——37017.61.71616512none
SPARC64 GP Fujitsu SFCB81147 400–563V920001×1=118030.2217——1.81281288192—
SPARC64 GP -- 600–810V9—1×1=115030.2———1.51281288192—
SPARC64 IV Fujitsu MBCS80523 450–810V920001×1=1130—————1281282048—
UltraSPARC III (Cheetah) Sun SME1050 600JPS120011×1=1180 Al293301368531.664328192none
UltraSPARC III (Cheetah) Sun SME1052 750–900JPS120011×1=1130 Al29—1368—1.664328192none
UltraSPARC III Cu (Cheetah+) Sun SME1056 900–1200JPS120011×1=1130 Cu29232136850[note 8]1.664328192none
UltraSPARC IIIi (Jalapeño) Sun SME1603 1064–1593JPS120031×1=113087.5206959521.364321024none
SPARC64 V (Zeus) Fujitsu 1100–1350JPS120031×1=1130190289269401.21281282048—
SPARC64 V+ (Olympus-B) Fujitsu 1650–2160JPS120041×1=1904002972796511281284096—
UltraSPARC IV (Jaguar) Sun SME1167 1050–1350JPS220041×2=21306635613681081.35643216384none
UltraSPARC IV+ (Panther) Sun SME1167A 1500–2100JPS220051×2=2902953361368901.16464204832768
UltraSPARC T1 (Niagara) Sun SME1905 1000–1400UA200520054×8=32903003401933721.38163072none
SPARC64 VI (Olympus-C) Fujitsu 2150–2400JPS220072×2=490540422—120–1501.1128×2128×24096–6144none
UltraSPARC T2 (Niagara 2) Sun SME1908A 1000–1600UA200720078×8=64655033421831951.1–1.58164096none
UltraSPARC T2 Plus (Victoria Falls) Sun SME1910A 1200–1600UA200720088×8=64655033421831——8164096none
SPARC64 VII (Jupiter)[23] Fujitsu 2400–2880JPS220082×4=865600445—150—64×464×46144none
UltraSPARC "RK" (Rock)[24] Sun SME1832 2300 ????canceled[25]2×16=3265 ?3962326 ? ?32322048 ?
SPARC64 VIIIfx (Venus)[26][27] Fujitsu 2000JPS2 / HPC-ACE20091×8=845760513127158 ?32×832×86144none
LEON2FT Atmel AT697F 100V820091×1=1180——19611.8/3.31632—none
SPARC T3 (Rainbow Falls) Oracle/Sun 1650UA200720108×16=12840[28] ????371 ?139 ?8166144none
Galaxy FT-1500 NUDT (China) 1800UA2007?201?8×16=12840 ???? ??? ?65 ?16×1616×16512×164096
SPARC64 VII+ (Jupiter-E or M3)[29][30] Fujitsu 2667–3000JPS220102×4=865———160—64×464×412288none
LEON3FT Cobham Gaisler GR712RC 100V8E20111×2=2180———1.5[note 9]1.8/3.34x4Kb4x4Kbnonenone
R1000 MCST (Russia) 1000JPS220111×4=490180128—151, 1.8, 2.532162048none
SPARC T4 (Yosemite Falls)[31] Oracle 2850–3000OSA201120118×8=6440855403 ?240 ?16×816×8128×84096
SPARC64 IXfx[32][33][34] Fujitsu 1850JPS2 / HPC-ACE20121x16=164018704841442110 ?32×1632×1612288none
SPARC64 X (Athena)[35] Fujitsu 2800OSA2011 / HPC-ACE20122×16=32282950587.51500270 ?64×1664×1624576none
SPARC T5 Oracle 3600OSA201120138×16=128281500478 ? ? ?16×1616×16128×168192
SPARC M5[36] Oracle 3600OSA201120138×6=48283900511 ? ? ?16×616×6128×649152
SPARC M6[37] Oracle 3600OSA201120138×12=96284270643 ? ? ?16×1216×12128×1249152
SPARC64 X+ (Athena+)[38] Fujitsu 3200–3700OSA2011 / HPC-ACE20142×16=322829906001500392 ?64×1664×1624Mnone
SPARC64 XIfx[39] Fujitsu 2200JPS2 / HPC-ACE220141×(32+2)=34203750 ?1001 ? ?64×3464×3412M×2none
SPARC M7[40][41] Oracle 4133OSA201520158×32=25620>10,000 ? ? ? ?16×3216×32256×2465536
SPARC S7[42][43] Oracle 4270OSA201520168×8=6420 ???? ? ? ? ?16×816×8256×2+256×416384
SPARC64 XII[44] Fujitsu 4250OSA201? / HPC-ACE20178×12=962055007951860 ? ?64×1264×12512×1232768
SPARC M8[45][46] Oracle 5000OSA201720178×32=25620 ? ? ? ? ?32×3216×32128×32+256×865536
LEON4 Cobham Gaisler GR740 250[note 10]V8E20171×4=432————1.2/2.5/3.34x44x42048none
R2000 MCST (Russia) 2000 ?20181×8=828500 ?— ? ? ? ? ?none
LEON5 Cobham Gaisler —V8E2019 ? ?————— ? ?16–8192none
Name (codename) Model Frequency (MHz) Arch. version Year Total threads[note 1] Process (nm) Transistors (millions) Die size (mm2) IO pins Power (W) Voltage (V) L1 Dcache (KB) L1 Icache (KB) L2 cache (KB) L3 cache (KB)
Close

Notes:

  1. [N 1]
    Threads per core × number of cores
  2. [N 2]
    Various SPARC V7 implementations were produced by Fujitsu, LSI Logic, Weitek, Texas Instruments, Cypress and Temic. A SPARC V7 processor generally consisted of several discrete chips, usually comprising an integer unit (IU), a floating-point unit (FPU), a memory management unit (MMU) and cache memory. Conversely, the Atmel (now Microchip Technology) TSC695 is a single-chip SPARC V7 implementation.
  3. [N 3]
    @167 MHz
  4. [N 4]
    @250 MHz
  5. [N 5]
    @400 MHz
  6. [N 6]
    @440 MHz
  7. [N 7]
    max. @500 MHz
  8. [N 8]
    @1200 MHz
  9. [N 9]
    excluding I/O buses
  10. [N 10]
    nominal; specification from 100 to 424 MHz depending on attached RAM capabilities

Operating system support

SPARC machines have generally used Sun's SunOS, Solaris, JavaOS, or OpenSolaris including derivatives illumos and OpenIndiana, but other operating systems have also been used, such as NeXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux.

In 1993, Intergraph announced a port of Windows NT to the SPARC architecture,[47] but it was later cancelled.

In October 2015, Oracle announced a "Linux for SPARC reference platform".[48]

Open source implementations

Several fully open source implementations of the SPARC architecture exist:

  • LEON, a 32-bit radiation-tolerant, SPARC V8 implementation, designed especially for space use. Source code is written in VHDL, and licensed under the GPL.
  • OpenSPARC T1, released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on existent open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary software license agreement.
  • S1, a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL.
  • OpenSPARC T2, released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

A fully open source simulator for the SPARC architecture also exists:

  • RAMP Gold, a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of SystemVerilog, and licensed under the BSD licenses.

Supercomputers

For HPC loads Fujitsu builds specialized SPARC64 fx processors with a new instruction extensions set, called HPC-ACE (High Performance Computing – Arithmetic Computational Extensions).

Fujitsu's K computer ranked No. 1 in the TOP500 June 2011 and November 2011 lists. It combines 88,128 SPARC64 VIIIfx CPUs, each with eight cores, for a total of 705,024 cores—almost twice as many as any other system in the TOP500 at that time. The K Computer was more powerful than the next five systems on the list combined, and had the highest performance-to-power ratio of any supercomputer system.[49] It also ranked No. 6 in the Green500 June 2011 list, with a score of 824.56 MFLOPS/W.[50] In the November 2012 release of TOP500, the K computer ranked No. 3, using by far the most power of the top three.[51] It ranked No. 85 on the corresponding Green500 release.[52] Newer HPC processors, IXfx and XIfx, were included in recent PRIMEHPC FX10 and FX100 supercomputers.

Tianhe-2 (TOP500 No. 1 as of November 2014[53]) has a number of nodes with Galaxy FT-1500 OpenSPARC-based processors developed in China. However, those processors did not contribute to the LINPACK score.[54][55]

See also

  • ERC32 — based on SPARC V7 specification
  • Ross Technology, Inc. — a SPARC microprocessor developer during the 1980s and 1990s
  • Sparcle — a modified SPARC with multiprocessing support used by the MIT Alewife project
  • LEON — a space rated SPARC V8 processor.
  • R1000 — a Russian quad-core microprocessor based on SPARC V9 specification
  • Galaxy FT-1500 — a Chinese 16-core OpenSPARC-based processor

References

External links

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