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Program status word

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The program status word[a] (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360[1] and its successors,[2][3][4][5][6] and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24[b] bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

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Format

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S/360

On all but 360/20,[c] the PSW has the following formats. S/360 Extended PSW format only applies to the 360/67 with bit 8 of control register 6 set.

More information Bits, Field ...

S/370

More information Bits, Field ...

S/370 Extended Architecture (S/370-XA)

More information Bits, Field ...

Enterprise Systems Architecture (ESA)

More information Bits, Field ...

z/Architecture

More information Bits, Field ...
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Notes

  1. The nomenclature varies among architectures.
  2. However, a 360/67[7] equipped with the Extended Dynamic Address Translation[8] feature has a 32-bit mode selected by bit 4 of the PSW[9] in Extended PSW mode[8] (Control Register 6, bit 8[10]).
  3. Despite the name, the 350/20 does not adhere to the S/360 architecture.
  4. Bit 22 is renamed as HFP exponent underflow in ESA/390
  5. Bit 23 is renamed as HFP significance in ESA/390
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References

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