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LISA (Language for Instruction Set Architectures) is a language to describe the instruction set architecture of a processor. LISA captures the information required to generate software tools (compiler, assembler, instruction set simulator, ...) and implementation hardware (in VHDL or Verilog) of a given processor.
| Designed by | Vojin Zivojnovic, Stefan Pees, version 1.0 |
|---|---|
| First appeared | 1997, last revised 2007 |
| Website | https://www.ice.rwth-aachen.de/research/tools-projects/closed-projects/lisa |
| Dialects | |
| LISA 2.0, LISA+ | |
LISA has been used to re-implement the hardware of existing processor cores, keeping the binary compatibility with the legacy version, as all software tools did already exist and legacy compiled software images could be executed on the newly created hardware. Another application has been to generate the ISS (instruction set simulator) for RISC processors such the ARM architecture ISSes.
LISA' is not focused on the modeling of other on-chip components around the processor core itself, such as peripherals, hardware accelerators, buses and memories; Other languages such as SystemC can be used for these.
The language has not been yet[as of?] standardised by IEEE or ISO and is currently owned by RWTH Aachen University, in Germany.
LISA was initially developed at Institute for Integrated Signal Processing Systems (ISS) Aachen, belonging to RWTH Aachen University, in Germany. The current official version from RWTH Aachen is LISA 2.0. The language is still in evolution to cover research on processors, including Reconfigurable computing (in LISA 3.0), multi-core, parallel programming.
One noticeable branch called LISA+ has been created for handling the modeling of peripherals such as interrupt controllers, timers, etc.[1]
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