ARM Cortex-A15
Family of microprocessor cores with ARM microarchitecture From Wikipedia, the free encyclopedia
The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz.[6]
| |
| General information | |
|---|---|
| Launched | In production late 2011,[1] to market late 2012[2] |
| Designed by | ARM Holdings |
| Performance | |
| Max. CPU clock rate | 1.0 GHz to 2.5 GHz |
| Cache | |
| L1 cache | 64 KB (32 KB I-cache, 32 KB D-cache) per core |
| L2 cache | Up to 4 MB[3] per cluster |
| L3 cache | none |
| Architecture and classification | |
| Technology node | 32 nm/28 nm initially[4] to 22 nm roadmap[4] |
| Instruction set | ARMv7-A |
| Physical specifications | |
| Cores |
|
Overview
Summarize
Perspective
ARM has claimed that the Cortex-A15 core is 40 percent more powerful than the Cortex-A9 core with the same number of cores at the same speed.[7] The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012.[1]
Key features of the Cortex-A15 core are:
- 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM with a 32-bit virtual address space.[8][9][10]
- 15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline[11]
- 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (CCI-400, an AMBA-4 coherent interconnect) and 4 clusters per chip with CCN-504.[12] ARM provides specifications but the licensees individually design ARM chips, and AMBA-4 scales beyond 2 clusters. The theoretical limit is 16 clusters; 4 bits are used to code the CLUSTERID number in the CP15 register (bits 8 to 11).[13]
- DSP and NEON SIMD extensions onboard (per core)
- VFPv4 Floating Point Unit onboard (per core)
- Hardware virtualization support
- Thumb-2 instruction set encoding to reduce the size of programs with little impact on performance
- TrustZone security extensions
- Jazelle RCT for JIT compilation
- Program Trace Macrocell and CoreSight Design Kit for unobtrusive tracing of instruction execution
- 32 KB data + 32 KB instruction L1 cache per core
- Integrated low-latency level-2 cache controller, up to 4 MB per cluster
Chips
Summarize
Perspective
First implementation came from Samsung in 2012 with the Exynos 5 Dual, which shipped in October 2012 with the Samsung Chromebook Series 3 (ARM version), followed in November by the Google Nexus 10.
Press announcements of current implementations:
- Broadcom SoC[14]
- HiSilicon K3V3[15]
- Nvidia Tegra 4 (Wayne)[16] and Tegra K1.
- Samsung Exynos 5 Dual, Quad and Octa[17]
- ST-Ericsson Nova A9600 (cancelled) (dual-core @ 2.5 GHz over 20k DMIPS)[18][19]
- Texas Instruments OMAP 5 SoCs[20] and Sitara AM57x family[21]
Other licensees, such as LG,[22][23] are expected to produce an A15 based design at some point.
Systems on a chip
| Model Number | Semiconductor technology | CPU | GPU | Memory interface | Wireless radio technologies | Availability | Utilizing devices |
|---|---|---|---|---|---|---|---|
| HiSilicon K3V3 | 28 nm HPL | big.LITTLE architecture using 1.8 GHz dual-core ARM Cortex-A15 + dual-core ARM Cortex-A7 |
Mali-T628 | H2 2014 | |||
| Nvidia Tegra 4 T40 | 28 nm HPL | 1.9 GHz quad-core ARM Cortex-A15[24] + 1 low power core | Nvidia GeForce @ 72 core, 672 MHz, 96.8 GFLOPS = 48 PS + 24 VU × 0.672 × 2 (96.8 GFLOPS)[25](support DirectX 11+, OpenGL 4.X, and PhysX) | 32-bit dual-channel DDR3L or LPDDR3 up to 933 MHz (1866 MT/s data rate)[24] | Category 3 (100 Mbit/s) LTE | Q2 2013 | Nvidia Shield Tegra Note 7 |
| Nvidia Tegra 4 AP40 | 28 nm HPL | 1.2-1.8 GHz quad-core + low power core | Nvidia GPU 60 [24] cores (support DirectX 11+, OpenGL 4.X, and PhysX) | 32-bit dual-channel 800 MHz LPDDR3 | Category 3 (100 Mbit/s) LTE | Q3 2013 | |
| Nvidia Tegra K1 | 28 nm HPm | 2.3 GHz quad-core + battery saver core | Kepler SMX (192 CUDA cores, 8 TMUs, 4 ROPs) | 32-bit dual-channel DDR3L, LPDDR3 or LPDDR2 | Q2 2014 | Jetson TK1 development board,[26] Lenovo ThinkVision 28, Xiaomi MiPad, Shield Tablet | |
| Texas Instruments OMAP5430 | 28 nm | 1.7 GHz dual-core | PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator | 32-bit dual-channel 532 MHz LPDDR2 | Q2 2013 | phyCore-OMAP5430[27] | |
| Texas Instruments OMAP5432 | 28 nm | 1.5 GHz dual-core | PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator | 32-bit dual-channel 532 MHz DDR3 | Q2 2013 | DragonBox Pyra, SVTronics EVM,[28] Compulab SBC-T54[29] | |
| Texas Instruments AM57x | 28 nm | 1.5 GHz single or dual-core | PowerVR SGX544MP2 @ 532 MHz + dedicated 2D graphics accelerator | 32-bit dual-channel 532 MHz DDR3 | Q4 2015 | BeagleBoard-X15,[30] BeagleBone AI,[31] Elesar Titanium[32] | |
| Texas Instruments 66AK2x | 28 nm | 1.5 GHz single, dual, and quad core devices | 1-8 C66x DSP cores, radio acceleration, and many other application specific accelerators | Q4 2015 | |||
| Exynos 5 Dual[33] (previously Exynos 5250)[34] |
32 nm HKMG | 1.7 GHz dual-core ARM Cortex-A15 | ARM Mali-T604[35] (quad-core) @ 533 MHz; 68.224 GFLOPS [citation needed] | 32-bit dual-channel 800 MHz LPDDR3/DDR3 (12.8 GB/sec) or 533 MHz LPDDR2 (8.5 GB/sec) | Q3 2012[34] | Samsung Chromebook XE303C12,[36] Google Nexus 10, Arndale Board,[37] Huins ACHRO 5250 Exynos,[38] Freelander PD800 HD,[39] Voyo A15, HP Chromebook 11, Samsung Homesync | |
| Exynos 5 Octa[40][41][42] (internally Exynos 5410) |
28 nm HKMG | 1.6 GHz[43] quad-core ARM Cortex-A15 and 1.2 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE)[44] | IT PowerVR SGX544MP3 (tri-core) @ 480 MHz 49 GFLOPS (532 MHz in some full-screen apps)[45] | 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) | Q2 2013 | Samsung Galaxy S4 I9500,[46][47] Hardkernel ODROID-XU,[48] Meizu MX3, ZTE Grand S II TD[49] ODROID-XU | |
| Exynos 5 Octa[50] (internally Exynos 5420) |
28 nm HKMG | 1.8-1.9 GHz quad-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) | ARM Mali-T628 MP6 @ 533 MHz; 109 GFLOPS | 32-bit dual-channel 933 MHz LPDDR3e (14.9 GB/sec) | Q3 2013 | Samsung Chromebook 2 11.6",[51] Samsung Galaxy Note 3,[52] Samsung Galaxy Note 10.1 (2014 Edition), Samsung Galaxy Note Pro 12.2, Samsung Galaxy Tab Pro (12.2 & 10.1), Arndale Octa Board, Galaxy S5 SM-G900H [53] | |
| Exynos 5 Octa[54] (internally Exynos 5422) |
28 nm HKMG | 2.1 GHz quad-core ARM Cortex-A15 and 1.5 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) | ARM Mali-T628 MP6 @ 695 MHz (142 Gflops) | 32-bit dual-channel 933 MHz LPDDR3/DDR3 (14.9 GB/sec) | Q2 2014 | Galaxy S5 SM-G900, Hardkernel ODROID-XU3 & ODROID-XU4[55] | |
| Exynos 5 Octa[56] (internally Exynos 5800) |
28 nm HKMG | 2.1 GHz quad-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) | ARM Mali-T628 MP6 @ 695 MHz (142 Gflops) | 32-bit dual-channel 933 MHz LPDDR3/DDR3 (14.9 GB/sec) | Q2 2014 | Samsung Chromebook 2 13,3"[57] | |
| Exynos 5 Hexa[58] (internally Exynos 5260) |
28 nm HKMG | 1.7 GHz dual-core ARM Cortex-A15 and 1.3 GHz quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) | ARM Mali-T624 | 32-bit dual-channel 800 MHz LPDDR3 (12.8 GB/sec) | Q2 2014 | Galaxy Note 3 Neo (announced January 31, 2014), Samsung Galaxy K zoom[59] | |
| Allwinner A80 Octa[60] | 28 nm HPm | Quad-core ARM Cortex-A15 and Quad-core ARM Cortex-A7 (ARM big.LITTLE with GTS) | PowerVR G6230 (Rogue) | 32-bit dual-channel DDR3/DDR3L/LPDDR3 or LPDDR2[61] | |||
See also
References
External links
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