PDP-11 architecture
Instruction set architecture developed by Digital Equipment Corporation / From Wikipedia, the free encyclopedia
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The PDP-11 architecture[1] is a 16-bit CISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX architecture in the 1980s.
Quick Facts Designer, Bits ...
Designer | Digital Equipment Corporation |
---|---|
Bits | 16-bit |
Introduced | 1970; 54 years ago (1970) |
Design | CISC |
Type | Register–register Register–memory Memory–memory |
Encoding | Variable (2 to 6 bytes) |
Branching | Condition code |
Endianness | Mixed (little-endian for 16-bit integers) |
Extensions | EIS, FIS, FPP, CIS |
Open | No |
Successor | VAX |
Registers | |
General-purpose | 8 × 16-bit |
Floating point | 6 × 64-bit floating-point registers if FPP present |
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