65 nm process
Advanced lithographic node used in volume CMOS semiconductor fabrication / From Wikipedia, the free encyclopedia
The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.[1]