P6 (microarchitecture)
Intel processor microarchitecture / From Wikipedia, the free encyclopedia
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The P6 microarchitecture is the sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995. It is frequently referred to as i686.[2] It was planned to be succeeded by the NetBurst microarchitecture used by the Pentium 4 in 2000, but was revived for the Pentium M line of microprocessors. The successor to the Pentium M variant of the P6 microarchitecture is the Core microarchitecture which in turn is also derived from P6.
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General information | |
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Launched | November 1, 1995; 28 years ago (November 1, 1995) |
Performance | |
Max. CPU clock rate | 150[1] MHz to 1.40 GHz |
FSB speeds | 66 MHz to 133 MHz |
Cache | |
L1 cache | Pentium Pro: 16 KB (8 KB I cache + 8 KB D cache) Pentium II/III: 32 KB (16 KB I cache + 16 KB D cache) |
L2 cache | 128 KB to 512 KB 256 KB to 2048 KB (Xeon) |
Architecture and classification | |
Microarchitecture | P6 |
Instruction set | x86-16, IA-32 |
Extensions | |
Physical specifications | |
Transistors | |
Cores |
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Socket(s) | |
Products, models, variants | |
Model(s) |
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Variant(s) |
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History | |
Predecessor(s) | P5 |
Successor(s) | NetBurst, Pentium M |
Support status | |
Unsupported |
P6 was used within Intel's mainstream offerings from the Pentium Pro to Pentium III, and was widely known for low power consumption, excellent integer performance, and relatively high instructions per cycle (IPC).