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Crossbar is a company based in Santa Clara, California.[1] Crossbar develops a class of non-volatile resistive random-access memory (RRAM) technology.[2]
| Company type | Privately held |
|---|---|
| Industry | Semiconductors: memory |
| Founded | 2010 |
| Founder | George Minassian, Hagop Nazarian, Wei Lu |
| Headquarters | |
| Products | Semiconductor Memory Technology |
Number of employees | 20+ |
Crossbar was founded in 2010, by George Minassian, Hagop Nazarian, and Wei Lu.[1][3] As part of the University of Michigan Tech Transfer program, in 2010, Crossbar licensed resistive RAM (RRAM) patents from the University of Michigan.[4] Crossbar filed patents relating to the development, commercialization and manufacturing of RRAM technology.[5]
In August 2013, Crossbar emerged from stealth mode and announced the development of a memory array at a commercial semiconductor device fabrication facility. It was said to deliver faster write performance; lower power consumption and more endurance at half the die size, compared to NAND flash memory. Since it is CMOS-compatible, it can be fabricated without special equipment or materials.[6]
Crossbar received $25 million in funding from Artiman Ventures, Kleiner Perkins Caufield and Byers, Northern Light Venture Capital and the Michigan Investment in New Technology Startups (MINTS) program in 2012.[7] Another funding round of about $35 million was announced in September 2015, with investors from China and Hong Kong.[8]
Crossbar primarily markets to original equipment manufacturers (OEMs) and system on a chip (SOC) developers of consumer, enterprise, mobile, industrial and Internet of things products.[9]
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The company in 2013 announced its goal was a terabyte of storage on a single RRAM integrated circuit, compatible with standard CMOS semiconductor manufacturing processes,[10] with a prototype showcased the same year having the theoretical ability to achieve this on a 200mm2 chip.[11][12] According to Crossbar, the chip uses a crosspoint array to stack multiple silver-ion-based memory layers on top of each other, with the prototype having three such layers.[13][14]
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